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fujitsu microelectronics data sheet copyright?2009 fujitsu microelectro nics limited all rights reserved 2009.8 for the information for microcontroller supports, see the following web site. this web site includes the "customer design review supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ 32-bit microcontroller cmos fr60 mb91460h series MB91F464HB description mb91460h series is a line of general-purpose 32-bit risc microcontrollers designed for embedded control applications which require high-speed real-time proces sing, such as consumer devices and on-board vehicle systems. this series uses the fr60 cpu, whic h is compatible with the fr family* of cpus. this series contains the li n-usart and can controllers. * : fr, the abbreviation of fujitsu risc controller, is a line of products of fujitsu microelectronics limited. features 1. fr60 cpu core ? 32-bit risc, load/store architecture, five-stage pipeline ? 16-bit fixed-length instruct ions (basic instructions) ? instruction execution speed: 1 instruction per cycle ? instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: instructions suitable for embedded applications ? function entry/exit instructions and register data multi-load store instructions : instructions supporting c language ? register interlock function: facilitating assembly-language coding ? built-in multiplier with in struction-level support signed 32-bit multiplication: 5 cycles signed 16-bit multiplication: 3 cycles ? interrupts (save pc/ps) : 6 cycles (16 priority levels) ? harvard architecture enabling program access and data access to be performed simultaneously ? instructions compatible with the fr family ds07-16616-1e
mb91460h series 2 ds07-16616-1e 2. internal peripheral resources ? general-purpose ports : maximum 108 ports ? dmac (dma controller) maximum of 5 channels able to operate simultaneously 2 transfer sources (internal peripheral/software) activation source can be selected using software addressing mode specifies full 32-bit addresses (increment/decrement/fixed) transfer mode (demand transfer/burst transfer/step transfer/block transfer) transfer data size selectable from 8/16/32-bit multi-byte transfer enabled (by software) dmac descriptor in i/o areas (200 h to 240 h , 1000 h to 1024 h ) ? a/d converter (successive approximation type) 10-bit resolution: maximum 32 channels conversion time: minimum 1 s ? external interrupt inputs : maximum 16 channels 3 channels shared with can rx or i 2 c pins ? bit search module (for realos) function to search the first bit position of ??1??, ??0??, ??changed?? from the msb (most significant bit) within one word ? lin-usart (full duplex double buffer): 4 or 7 channels clock synchronous/asyn chronous selectable sync-break detection internal dedicated baud rate generator ?i 2 c bus interface (supports 400 kbps): 2 channels master/slave transmission and reception arbitration function, clock synchronization function ? can controller (c-can): 1 channel maximum transfer speed: 1 mbps 32 transmission/reception message buffers ? sound generator : 1 channel tone frequency : pwm frequency divide-by-two (reload value + 1) ? alarm comparator : 1 channel monitor external voltage generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage) ? 16-bit ppg timer : maximum 16 channels ? 16-bit reload timer: 8 channels ? 16-bit free-run timer: 8 channels (1 channel each for icu and ocu) ? input capture: maximum 8 channels (operates in conjunction with the free-run timer) ? output compare: maximum 8 channels (operates in conjunction with the free-run timer) ? up/down counter: 2 channels (2*8-bit or 1*16-bit) ? watchdog timer ? real-time clock ? low-power consumption modes : sleep/stop mode function ? low voltage detection circuit (continued)
mb91460h series ds07-16616-1e 3 (continued) ? clock supervisor monitors the sub-clock (32 khz) and the main clock (4 mhz) , and switches to a recovery clock (cr oscillator, etc.) when the oscillations stop. ? clock modulator ? clock monitor ? sub-clock calibration corrects the real-time clock timer when o perating with the 32 khz or cr oscillator ? main oscillator stabilization timer generates an interrupt in sub-clock mo de after the stabilization wait time has elapsed on the 23-bit stabilization wait time counter ? sub-oscillator stabilization timer generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time counter 3. package and technology ? package : qfp-144 ? cmos 180 nm technology ? power supply range 3 v to 5 v (1.8 v internal logic provided by a step-down voltage converter) ? operating temperature range: between - 40c and + 105c
mb91460h series 4 ds07-16616-1e product lineup feature mb91fv460b MB91F464HB max. core frequency (clkb) 100 mhz 100 mhz max. resource frequency (clkp) 50 mhz 50 mhz max. external bus freque ncy (clkt) 50 mhz 50 mhz max. can frequency (clkcan) 50 mhz 50 mhz technology 0.18 + + = = = = = = + = = = + = = =
mb91460h series ds07-16616-1e 5 external interrupts 32 ch md_3=0: 16 ch md_3=1: 12 ch *9 nmi interrupts 1 ch 1 ch adc (10-bit) 32 ch + 22 ch md_3=0: 32 ch md_3=1: 16 ch alarm comparator 2 ch 1 ch supply supervisor (low voltage detection) yes yes clock supervisor yes yes main clock oscillator 4 mhz 4 mhz sub clock oscillator 32khz 32khz rc oscillator 100khz / 2mhz 100khz / 2mhz pll x 25 x 25 dsu4 yes no edsu yes (32 bp) *1 yes (16 bp) *1 supply voltage 1.8v + 3v/5v 3v/5v regulator no yes power consumption 1.5 w < 1 w temperature range (ta) 0..70 c -40..105 c package bga-896 qfp-144 power on to pll run < 20 ms < 20 ms flash download time < 8 sec. typical < 5 sec. typical feature mb91fv460b MB91F464HB
mb91460h series 6 ds07-16616-1e pin assignment 1. MB91F464HB with md_3=1 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 vdd5 avcc5 avrh5 avss5 alarm_0 p18_6/ sck7/ ck7 p18_5/ sot7 p18_4/ sin7 p18_2/ sck6/ ck6 p18_1/ sot6 p18_0/ sin6 p19_6/ sck5/ ck5 p19_5/ sot5 p19_4/ sin5 p19_2/ sck4/ ck4 p19_1/ sot4 p19_0/ sin4 vss5 vdd5 vdd5r vdd5r vcc18c vss5 nmix initx x1a x0a vss5 x0 x1 md_3 monclk md_2 md_1 md_0 vss5 vss5 p07_6/ a6 p07_7/ a7 p06_0/ a8 p06_1/ a9 p06_2/ a10 p06_3/ a11 p06_4/ a12 p06_5/ a13 p06_6/ a14 p06_7/ a15 p05_0/ a16 p05_1/ a17 p05_2/ a18 p05_3/ a19 p05_4/ a20 p05_5/ a21 vdd35 vss5 p01_0/ d16 p01_1/ d17 p01_2/ d18 p01_3/ d19 p01_4/ d20 p01_5/ d21 p01_6/ d22 p01_7/ d23 p00_0/ d24 p00_1/ d25 p00_2/ d26 p00_3/ d27 p00_4/ d28 p00_5/ d29 p00_6/ d30 p00_7/ d31 vdd35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vdd35 p07_5/ a5 p07_4/ a4 p07_3/ a3 p07_2/ a2 p07_1/ a1 p07_0/ a0 p15_3/ ocu3/ tot3 p15_2/ ocu2/ tot2 p15_1/ ocu1/ tot1 p15_0/ ocu0/ tot0 p14_3/ icu3/ tin3/ ttg3/ 11 p14_2/ icu2/ tin2/ ttg2/ 10 p14_1/ icu1/ tin1/ ttg1/ 9 p14_0/ icu0/ tin0/ ttg0/ 8 p24_3/ int3 p24_2/ int2 vss5 vdd5 p28_7/ an15 p28_6/ an14 p28_5/ an13 p28_4/ an12 p28_3/ an11 p28_2/ an10 p28_1/ an9 p28_0/ an8 p29_7/ an7 p29_6/ an6 p29_5/ an5 p29_4/ an4 p29_3/ an3 p29_2/ an2 p29_1/ an1 p29_0/ an0 vss5 vss5 p10_0/ sysclk p09_0/ csx0 p09_1/ csx1 p08_0/ wrx0 p08_4/ rdx p08_7/ rdy p08_1/ wrx1 p24_1/ int1 p23_0/ rx0/ int8 p23_1/ tx0 p23_2/ int9 p23_3 p23_4int10 p23_5 p23_6/ int11 p23_7 vdd5 vss5 p22_0/ int12 p22_1 p22_2/ int13 p22_3 p22_4/ sda0/ int14 p22_5/ scl0 p22_6/ sda1/ int15 p22_7/ scl1 p16_0/ ppg8 p16_1/ ppg9 p16_2/ ppg10 p16_3/ ppg11 p16_4/ ppg12/ sga p16_5/ ppg13/ sgo p16_6/ ppg14 p16_7/ ppg15/ atgx vdd5 lqfp-144
mb91460h series ds07-16616-1e 7 2. mb91f46hb with md_3=0 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 vdd5 avcc5 avrh5 avss5 alarm_0 p18_6/ sck7/ ck 7 p18_5/ sot7 p18_4/ sin7 p18_2/ sck6/ ck 6 p18_1/ sot6 p18_0/ sin6 p19_6/ sck5/ ck 5 p19_5/ sot5 p19_4/ sin5 p19_2/ sck4/ ck 4 p19_1/ sot4 p19_0/ sin4 vss5 vdd5 vdd5r vdd5r vcc18c vss5 nmix initx x1a x0a vss5 x0 x1 md_3 monclk md_2 md_1 md_0 vss5 vss5 p27_6/ an22 p27_7/ an23 p26_0/ an24 p26_1/ an25 p26_2/ an26 p26_3/ an27 p26_4/ an28 p26_5/ an29 p26_6/ an30 p26_7/ an31 p24_4/ int4 p24_5/ int5 p24_6/ int6 p24_7/ int7 p21_0/ sin0 p21_1/ sot0 vdd35 vss5 p14_4/ icu4/ tin4/ ttg12/ 4 p14_5/ icu5/ tin5/ ttg13/ 5 p14_6/ icu6/ tin6/ ttg14/ 6 p14_7/ icu7/ tin7/ ttg15/ 7 p15_4/ ocu4/ tot4 p15_5/ ocu5/ tot5 p15_6/ ocu6/ tot6 p15_7/ ocu7/ tot7 p17_0/ ppg0 p17_1/ ppg1 p17_2/ ppg2 p17_3/ ppg3 p17_4/ ppg4 p17_5/ ppg5 p17_6/ ppg6 p17_7/ ppg7 vdd35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vdd35 p27_5/ an21 p27_4/ an20 p27_3/ an19 p27_2/ an18 p27_1/ an17 p27_0/ an16 p15_3/ ocu3/ tot3 p15_2/ ocu2/ tot2 p15_1/ ocu1/ tot1 p15_0/ ocu0/ tot0 p14_3/ icu3/ tin3/ ttg3/ 11 p14_2/ icu2/ tin2/ ttg2/ 1 0 p14_1/ icu1/ tin1/ ttg1/ 9 p14_0/ icu0/ tin0/ ttg0/ 8 p24_3/ int3 p24_2/ int2 vss5 vdd5 p28_7/ an15 p28_6/ an14 p28_5/ an13 p28_4/ an12 p28_3/ an11 p28_2/ an10 p28_1/ an9 p28_0/ an8 p29_7/ an7 p29_6/ an6 p29_5/ an5 p29_4/ an4 p29_3/ an3 p29_2/ an2 p29_1/ an1 p29_0/ an0 vss5 vss5 p20_0/ sin2/ ain0 p20_1/ sot2/ bin0 p20_2/ sck2/ zin0/ ck2 p20_4/ sin3/ ain1 p20_5/ sot3/ bin1 p20_6/ sck3/ zin1/ ck3 p24_0/ int0 p24_1/ int1 p23_0/ rx0/ int8 p23_1/ tx0 p23_2/ int9 p23_3 p23_4/ int10 p23_5 p23_6/ int11 p23_7 vdd5 vss5 p22_0/ int12 p22_1 p22_2/ int13 p22_3 p22_4/ sda0/ int14 p22_5/ scl0 p22_6/ sda1/ int15 p22_7/ scl1 p16_0/ ppg8 p16_1/ ppg9 p16_2/ ppg10 p16_3/ ppg11 p16_4/ ppg12/ sga p16_5/ ppg13/ sgo p16_6/ ppg14 p16_7/ ppg15/ atgx vdd5 lqfp-144
mb91460h series 8 ds07-16616-1e pin description 1. MB91F464HB with md_3=1 pin no. pin name i/o i/o circuit type* function 2, 3 p07_6, p07_7 i/o b general-purpose input/output port a6, a7 signal pins of external address bus (bit6 to bit7) 4 to 11 p06_0 to p06_7 i/o b general-purpose input/output port a8 to a15 signal pins of external address bus (bit8 to bit15) 12 to 17 p05_0 to p05_5 i/o a general-purpose input/output port a16 to a21 signal pins of external address bus (bit16 to bit21) 20 to 27 p01_0 to p01_7 i/o a general-purpose input/output port d16 to d23 signal pins of external data bus (bit16 to bit23) 28 to 35 p00_0 to p00_7 i/o a general-purpose input/output port d24 to d31 signal pins of external data bus (bit24 to bit31) 38 p10_0 i/o a general-purpose input/output port sysclk external bus clock output pin 39 p09_0 i/o a general-purpose input/output port csx0 chip select output pins 40 p09_1 i/o a general-purpose input/output port csx1 chip select output pins 41 p08_0 i/o a general-purpose input/output port wrx0 external write strobe output pins 42 p08_4 i/o a general-purpose input/output port rdx external read strobe output pin 43 p08_7 i/o a general-purpose input/output port rdy external ready input pin 44 p08_1 i/o a general-purpose input/output port wrx1 external write strobe output pins int0 external interrupt input, can only be used in general-purpose io port mode 45 p24_1 i/o a general-purpose input/output port int1 external interrupt input pins 46 p23_0 i/o a general-purpose input/output port rx0 rx input pin of can0 int8 external interrupt input pins 47 p23_1 i/o a general-purpose input/output port tx0 tx output pin of can0
mb91460h series ds07-16616-1e 9 48 p23_2 i/o a general-purpose input/output port int9 external interrupt input pins 49 p23_3 i/o a general-purpose input/output port 50 p23_4 i/o a general-purpose input/output port int10 external interrupt input pin 51 p23_5 i/o a general-purpose input/output port 52 p23_6 i/o a general-purpose input/output port int11 external interrupt input pin 53 p23_7 i/o a general-purpose input/output port 56 p22_0 i/o a general-purpose input/output port int12 external interrupt input pin 57 p22_1 i/o a general-purpose input/output port 58 p22_2 i/o a general-purpose input/output port int13 external interrupt input pin 59 p22_3 i/o a general-purpose input/output port 60 p22_4 i/o c general-purpose input/output port sda0 i 2 c bus data input/output pin (open drain) int14 external interrupt input pin 61 p22_5 i/o c general-purpose input/output port scl0 i 2 c bus clock input/output pin (open drain) 62 p22_6 i/o c general-purpose input/output port sda1 i 2 c bus data input/output pin (open drain) int15 external interrupt input pin 63 p22_7 i/o c general-purpose input/output port scl1 i 2 c bus clock input/output pin (open drain) 64 p16_0 i/o a general-purpose input/output port ppg8 output pins of ppg timer 65 p16_1 i/o a general-purpose input/output port ppg9 output pins of ppg timer 66 p16_2 i/o a general-purpose input/output port ppg10 output pins of ppg timer 67 p16_3 i/o a general-purpose input/output port ppg11 output pins of ppg timer 68 p16_4 i/o a general-purpose input/output port ppg12 output pins of ppg timer sga sga output pin of sound generator pin no. pin name i/o i/o circuit type* function
mb91460h series 10 ds07-16616-1e 69 p16_5 i/o a general-purpose input/output port ppg13 output pins of ppg timer sgo sgo output pin of sound generator 70 p16_6 i/o a general-purpose input/output port ppg14 output pins of ppg timer 71 p16_7 i/o a general-purpose input/output port ppg15 output pins of ppg timer atgx a/d converter external trigger input pin 74 to 76 md_0 to md_2 i g mode setting pins 77 monclk o m clock monitor pin 78 md_3 i h mode setting pin 79 x1 ? j1 clock (oscillation) output 80 x0 ? j1 clock (oscillation) input 82 x0a ? j2 sub clock (oscillation) input 83 x1a ? j2 sub clock (oscillation) output 84 initx i h external reset input pin 85 nmix i h non-maskable interrupt input pin 92 p19_0 i/o a general-purpose input/output port sin4 data input pin of usart4 93 p19_1 i/o a general-purpose input/output port sot4 data output pin of usart4 94 p19_2 i/o a general-purpose input/output port sck4 clock input/output pin of usart4 ck4 external clock input pin of free-run timer 4 95 p19_4 i/o a general-purpose input/output port sin5 data input pin of usart5 96 p19_5 i/o a general-purpose input/output port sot5 data output pin of usart5 97 p19_6 i/o a general-purpose input/output port sck5 clock input/output pin of usart5 ck5 external clock input pin of free-run timer 5 98 p18_0 i/o a general-purpose input/output port sin6 data input pin of usart6 99 p18_1 i/o a general-purpose input/output port sot6 data output pin of usart6 pin no. pin name i/o i/o circuit type* function
mb91460h series ds07-16616-1e 11 100 p18_2 i/o a general-purpose input/output port sck6 clock input/output pin of usart6 ck6 external clock input pin of free-run timer 6 101 p18_4 i/o a general-purpose input/output port sin7 data input pin of usart7 102 p18_5 i/o a general-purpose input/output port sot7 data output pin of usart7 103 p18_6 i/o a general-purpose input/output port sck7 clock input/output pin of usart7 ck7 external clock input pin of free-run timer 7 104 alarm_0 i n alarm comparator input pin 110 to 117 p29_0 to p29_7 i/o b general-purpose input/output port an0 to an7 analog input pins of a/d converter 118 to 125 p28_0 to p28_7 i/o b general-purpose input/output port an8 to an15 analog input pins of a/d converter 128 p24_2 i/o a general-purpose input/output port int2 external interrupt input pin 129 p24_3 i/o a general-purpose input/output port int3 external interrupt input pin 130 to 133 p14_0 to p14_3 i/o a general-purpose input/output port icu0 to icu3 input capture input pins tin0 to tin3 external trigger input pins of reload timer ttg0/8 to ttg3/11 external trigger input pins of ppg timer 134 to 137 p15_0 to p15_3 i/o a general-purpose input/output port ocu0 to ocu3 output compare output pins tot0 to tot3 reload timer output pins 138 to 143 p07_0 to p07_5 i/o b general-purpose input/output port a0 to a5 signal pins of external address bus (bit0 to bit5) pin no. pin name i/o i/o circuit type* function
mb91460h series 12 ds07-16616-1e [power supply/ground pins] pin no. pin name i/o function 1, 19, 37, 55, 73, 81, 86, 91, 109, 127 vss5 supply ground pins 54, 72, 90, 108, 126 vdd5 power supply pins 88, 89 vdd5r power supply pins for internal regulator 105 avss5 analog ground pin for a/d converter 107 avcc5 power supply pin for a/d converter 106 avrh5 reference power supply pin for a/d converter 87 vcc18c capacitor connection pin for internal regulator 18, 36, 144 vdd35 power supply pins for external bus part of i/o ring
mb91460h series ds07-16616-1e 13 2. MB91F464HB with md_3=0 pin no. pin name i/o i/o circuit type* function 2 to 3 p27_6 to p27_7 i/o b general-purpose input/output ports an22 to an23 analog input pins of a/d converter 4 to 11 p26_0 to p26_7 i/o b general-purpose input/output ports an24 to an31 analog input pins of a/d converter 12 to 15 p24_4 to p24_7 i/o a general-purpose input/output ports int4 to int7 external interrupt input pins 16 p21_0 i/o a general-purpose input/output ports sin0 data input pin of usart0 17 p21_1 i/o a general-purpose input/output ports sot0 data output pin of usart0 20 to 23 p14_4 to p14_7 i/o a general-purpose input/output ports icu4 to icu7 input capture input pins tin4 to tin7 external trigger input pins of reload timer ttg4/12 to ttg7/15 external trigger input pins of ppg timer 24 to 27 p15_4 to p15_7 i/o a general-purpose input/output ports ocu4 to ocu7 output compare output pins tot4 to tot7 reload timer output pins 28 to 35 p17_0 to p17_7 i/o a general-purpose input/output ports ppg0 to ppg7 output pins of ppg timer 38 p20_0 i/o a general-purpose input/output ports sin2 data input pin of usart2 ain0 up/down counter input pin 39 p20_1 i/o a general-purpose input/output ports sot2 data output pin of usart2 bin0 up/down counter input pin 40 p20_2 i/o a general-purpose input/output ports sck2 clock input/output pin of usart2 zin0 up/down counter input pin ck2 external clock input pin of free-run timer 2 41 p20_4 i/o a general-purpose input/output ports sin3 data input pin of usart3 ain1 up/down counter input pin 42 p20_5 i/o a general-purpose input/output ports sot3 data output pin of usart3 bin1 up/down counter input pin
mb91460h series 14 ds07-16616-1e 43 p20_6 i/o a general-purpose input/output ports sck3 clock input/output pin of usart3 zin1 up/down counter input pin ck3 external clock input pin of free-run timer 3 44 p24_0 i/o a general-purpose input/output ports int0 external interrupt input pin 45 p24_1 i/o a general-purpose input/output ports int1 external interrupt input pin 46 p23_0 i/o a general-purpose input/output port rx0 rx input pin of can0 int8 external interrupt input pins 47 p23_1 i/o a general-purpose input/output port tx0 tx output pin of can0 48 p23_2 i/o a general-purpose input/output port int9 external interrupt input pins 49 p23_3 i/o a general-purpose input/output port 50 p23_4 i/o a general-purpose input/output port int10 external interrupt input pin 51 p23_5 i/o a general-purpose input/output port 52 p23_6 i/o a general-purpose input/output port int11 external interrupt input pin 53 p23_7 i/o a general-purpose input/output port 56 p22_0 i/o a general-purpose input/output port int12 external interrupt input pin 57 p22_1 i/o a general-purpose input/output port 58 p22_2 i/o a general-purpose input/output port int13 external interrupt input pin 59 p22_3 i/o a general-purpose input/output port 60 p22_4 i/o c general-purpose input/output ports sda0 i 2 c bus data input/output pin (open drain) int14 external interrupt input pin 61 p22_5 i/o c general-purpose input/output ports scl0 i 2 c bus clock input/output pin (open drain) 62 p22_6 i/o c general-purpose input/output ports sda1 i 2 c bus data input/output pin (open drain) int15 external interrupt input pin pin no. pin name i/o i/o circuit type* function
mb91460h series ds07-16616-1e 15 63 p22_7 i/o c general-purpose input/output ports scl1 i 2 c bus clock input/output pin (open drain) 64 to 67 p16_0 to p16_3 i/o a general-purpose input/output ports ppg8 to ppg11 output pins of ppg timer 68 p16_4 i/o a general-purpose input/output ports ppg12 output pins of ppg timer sga sga output pin of sound generator 69 p16_5 i/o a general-purpose input/output ports ppg13 output pins of ppg timer sgo sgo output pin of sound generator 70 p16_6 i/o a general-purpose input/output ports ppg14 output pins of ppg timer 71 p16_7 i/o a general-purpose input/output ports ppg15 output pins of ppg timer atgx a/d converter external trigger input pin 74 to 76 md_0 to md_2 i g mode setting pins 77 monclk o m clock monitor pin 78 md_3 i h mode setting pins 79 x1 ? j1 clock (oscillation) output 80 x0 ? j1 clock (oscillation) input 82 x0a ? j2 sub clock (oscillation) input 83 x1a ? j2 sub clock (oscillation) output 84 initx i h external reset input pin 85 nmix i h non-maskable interrupt input pin 92 p19_0 i/o a general-purpose input/output ports sin4 data input pin of usart4 93 p19_1 i/o a general-purpose input/output ports sot4 data output pin of usart4 94 p19_2 i/o a general-purpose input/output ports sck4 clock input/output pin of usart4 ck4 external clock input pin of free-run timer 4 95 p19_4 i/o a general-purpose input/output ports sin5 data input pin of usart5 96 p19_5 i/o a general-purpose input/output ports sot5 data output pin of usart5 pin no. pin name i/o i/o circuit type* function
mb91460h series 16 ds07-16616-1e * : for information about the i/o circuit type, refer to ? i/o circuit types?. 97 p19_6 i/o a general-purpose input/output ports sck5 clock input/output pin of usart5 ck5 external clock input pin of free-run timer 5 98 p18_0 i/o a general-purpose input/output ports sin6 data input pin of usart6 99 p18_1 i/o a general-purpose input/output ports sot6 data output pin of usart6 100 p18_2 i/o a general-purpose input/output ports sck6 clock input/output pin of usart6 ck6 external clock input pin of free-run timer 6 101 p18_4 i/o a general-purpose input/output ports sin7 data input pin of usart7 102 p18_5 i/o a general-purpose input/output ports sot7 data output pin of usart7 103 p18_6 i/o a general-purpose input/output ports sck7 clock input/output pin of usart7 ck7 external clock input pin of free-run timer 7 104 alarm_0 i n alarm comparator input pin 110 to 117 p29_0 to p29_7 i/o b general-purpose input/output ports an0 to an7 analog input pins of a/d converter 118 to 125 p28_0 to p28_7 i/o b general-purpose input/output ports an8 to an15 analog input pins of a/d converter 128 p24_2 i/o a general-purpose input/output ports int2 external interrupt input pin 129 p24_3 i/o a general-purpose input/output ports int3 external interrupt input pin 130 to 133 p14_0 to p14_3 i/o a general-purpose input/output ports icu0 to icu3 input capture input pins tin0 to tin3 external trigger input pins of reload timer ttg0/8 to ttg3/11 external trigger input pins of ppg timer 134 to 137 p15_0 to p15_3 i/o a general-purpose input/output ports ocu0 to ocu3 output compare output pins tot0 to tot3 reload timer output pins 138 to 143 p27_0 to p27_5 i/o b general-purpose input/output ports an16 to an21 analog input pins of a/d converter pin no. pin name i/o i/o circuit type* function
mb91460h series ds07-16616-1e 17 [power supply/ground pins] * : for information about the i/o circuit type, refer to ? i/o circuit types?. pin no. pin name i/o function 1, 19, 37, 55, 73, 81, 86, 91, 109, 127 vss5 supply ground pins 54, 72, 90, 108, 126 vdd5 power supply pins 88, 89 vdd5r power supply pins for internal regulator 105 avss5 analog ground pin for a/d converter 107 avcc5 power supply pin for a/d converter 106 avrh5 reference power supply pin for a/d converter 87 vcc18c capacitor connection pin for internal regulator 18, 36, 144 vdd35 power supply pins for external bus part of i/o ring
mb91460h series 18 ds07-16616-1e i/o circuit types type circuit remarks a cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k = = = = pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown r analog input pull-up control pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown
mb91460h series ds07-16616-1e 19 c cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k approx. d cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k approx. analog input type circuit remarks pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control data line standby control for input shutdown r analog input pull-up control pull- down control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown
mb91460h series 20 ds07-16616-1e e cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma, and i ol = 30ma, i oh = -30ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k approx. f cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma, and i ol = 30ma, i oh = -30ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k approx. analog input type circuit remarks pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown r analog input pull-up control pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown
mb91460h series ds07-16616-1e 21 g mask rom and eva device: cmos hysteresis input pin flash device: cmos input pin 12 v withstand (for md [2:0]) h cmos hysteresis input pin pull-up resistor value: 50 k approx. j1 high-speed oscillation circuit: ? programmable between oscillation mode (external crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (external clock connected to x0 pin) ? feedback resistor = approx. 2 * 0.5 m . feedback resistor is grounded in the center when the oscillator is disabled or in fci mode. j2 low-speed oscillation circuit: ? feedback resistor = approx. 2 * 5 m . feedback resistor is grounded in the center when the oscillator is disabled. type circuit remarks r hysteresis inputs r pull-up resistor hysteresis inputs x1 x0 r r xout fci 0 1 fci or osc disable x1a x0a r r xout osc disable
mb91460h series 22 ds07-16616-1e k cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k approx. lcd seg/com output l cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function) ttl input with input shutdown function programmable pull-up resistor: 50k approx. analog input lcd voltage input type circuit remarks pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown lcd seg/com r pull-up control pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown vlcd
mb91460h series ds07-16616-1e 23 m cmos level tri-state output (i ol = 5ma, i oh = -5ma) n analog input pin with protection type circuit remarks tri-state control data line analog input line
mb91460h series 24 ds07-16616-1e handling devices 1. preventing latch-up latch-up may occur in a cmos ic if a voltage higher than (v dd 5, v dd 35 or hv dd 5 * 1 ) or less than (v ss 5 or hv ss 5 * 1 ) is applied to an input or output pin or if a vo ltage exceeding the rating is applied between the power supply pins and ground pins. if latch-up occurs, the powe r supply current increases rapidly, sometimes resulting in thermal breakdown of the device. therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. note *1: hv dd 5, hv ss 5 are available only on devices having stepper motor controller. 2. handling of unused input pins if unused input pins are left open, abnormal operation may result. any unused input pins should be connected to pull-up or pull- down resistor (2k 3. power supply pins in mb91460 series, devices including multiple power supp ly pins and ground pins are designed as follows; pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up. all of the power supply pins and ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal ma lfunctions due to the ground level rising and to follow the total output current ratings. furthermore, the power supply pins and ground pins of the mb91460 series must be connected to the current supply source via a low impedance. it is also recommended to connect a ceramic capacitor of approximately 0.1 4. crystal oscillator circuit noise in proximity to the x0 (x0a) and x1 (x1a) pins c an cause the device to operate abnormally. printed circuit boards should be designed so that the x0 (x0a) and x1 (x1a) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. it is recommended that the printed circuit board layout be designed such that the x0 and x1 pins or x0a and x1a pins are surrounded by ground plane for the stable operation. please request the oscillator manufacturer to evaluate the oscillational charac teristics of the crystal and this device. 5. notes on using external clock when using the external clock, it is necessary to simu ltaneously supply the x0 (x0a) and the x1 (x1a) pins. in the described combination, x1 (x1a) should be supplie d with a clock signal whic h has the opposite phase to the x0 (x0a) pins. at x0 and x1, a frequency up to 16 mhz is possible. (continued)
mb91460h series ds07-16616-1e 25 (continued) example of using opposite phase supply 6. mode pins (md_x) these pins should be connected directly to the power supp ly or ground pins. to prevent the device from entering test mode accidentally due to noise, minimize the le ngths of the patterns between each mode pin and power supply pin or ground pin on the printed circuit bo ard as possible and connect them with low impedance. 7. notes on operating in pll clock mode if the oscillator is disconnected or th e clock input stops when the pll clock is selected, the microcontroller may continue to operate at the free-runni ng frequency of the self-o scillating circuit of the pll. however, this self- running operation cannot be guaranteed. 8. pull-up control the ac standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin. x0 (x0a) x1 (x1a)
mb91460h series 26 ds07-16616-1e notes on debugger 1. execution of the reti command if single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling routine will be exec uted repeatedly to the exclusion of other processing. this will prevent the main routine and the handlers for low priority level interrupts from being executed (for example, if the time-base timer interrupt is enab led, stepping over the reti in struction will always break on the first line of the time-base timer interrup t handler). disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debug- ging. 2. break function if the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack pointer or to an area that contains the sta ck pointer, execution will break after each instruction regardless of whether the user progra m actually contains data access instructions. to prevent this, do not set (word) access to the area c ontaining the address of the system stack pointer as the target of the hardware break (including an event breaks). 3. operand break it may cause malfunctions if a stack pointer exists in the area which is set as the dsu operand break. do not set the access to the areas containing the address of system stack pointer as a target of data event break. 4. notes on ps register as the ps register is processed in ad vance by some instructions, when the debugger is being used, the exception handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in the ps register being updated. as the microcontroller is designed to carry out reprocessing correctly upon returning from such an eit event, the operation before and after the eit always proceeds according to specification. ? the following behavior may occur if any of the following occurs in the instruction immediately after a div0u/div0s instruction: (a) a user interrupt or nmi is accepted; (b) single-step execution is performed; (c) execution breaks due to a data event or from the emulator menu. 1. d0 and d1 flags are updated in advance. 2. an eit handling routine (user inte rrupt/nmi or emulator) is executed. 3. upon returning from the eit, the div0u/div0s instruct ion is executed and the d0 and d1 flags are updated to the same values as those in 1. ? the following behavior occurs when an orccr, stilm, mov ri,ps instruction is executed to enable a user interrupt or nmi source while that interrupt is in the active state. 1. the ps register is updated in advance. 2. an eit handling routine (user inte rrupt/nmi or emulator) is executed. 3. upon returning from the eit, the above in structions are executed and the ps register is updated to the same value as in 1.
mb91460h series ds07-16616-1e 27 block diagram 1. MB91F464HB with md_3=1 ttg0/8 to ttg3/11 ppg8 to ppg15 tin0 to tin3 tot0 to tot3 ck4 to ck7 icu0 to icu3 ocu0 to ocu3 alarm_0 sda0 to sda1 scl0 to scl1 an0 to an15 atgx sga sgo sin4 to sin7 sot4 to sot7 sck4 to sck7 rx0 tx0 r-bus 16 i-bus 32 d-bus 32 fr60 cpu core flash-cache 8 kbytes flash memory 416 kbytes (MB91F464HB) id-ram 16 kbytes bus converter d-ram 16 kbytes bit search can 1 channel 32 <-> 16 bus adapter dmac 5 channels clock modulator clock monitor monclk interrupt controller int0 to int3, int8 to to int15 external interrupt 12 channels clock supervisor clock control ppg timer 8 channels reload timer 8 channels free-run timer 8 channels input capture 4 channels output compare 4 channels alarm comparator 1 channel lin-usart 4 channels 2 channels i c 2 real time clock a/d converter 16 channels sound generator 1 channel rdx wrx0 to wrx1 csx0 to csx1 a0 to a21 d16 to d31 external bus interface sysclk rdy
mb91460h series 28 ds07-16616-1e 2. MB91F464HB with md_3=0 ain0 to ain1 bin0 to bin1 zin0 to zin1 ttg0/8 to ttg7/15 ppg0 to ppg15 tin0 to tin7 tot0 to tot7 ck2 to ck7 icu0 to icu7 ocu0 to ocu7 alarm_0 sda0 to sda1 scl0 to scl1 an0 to an31 atgx sga sgo sin2 to sin7,sin0 sot2 to sot7,sot0 sck2 to sck7 rx0 tx0 r-bus 16 i-bus 32 d-bus 32 fr60 cpu core flash-cache 8 kbytes flash memory 416 kbytes (MB91F464HB) id-ram 16 kbytes bus converter d-ram 16kbytes bit search can 1 channel 32 <-> 16 bus adapter dmac 5 channels clock modulator clock monitor monclk interrupt controller int0 to int15 external interrupt 16 channels clock supervisor clock control ppg timer 16 channels reload timer 8 channels free-run timer 8 channels input capture 8 channels output compare 8 channels up/down counter 2 channels alarm comparator 1 channel lin-usart 7 channels 2 channels i c 2 real time clock a/d converter 32 channels sound generator 1 channel
mb91460h series ds07-16616-1e 29 cpu and control unit the fr family cpu is a high performance core that is designed based on the risc architecture with advanced instructions for embedded applications. 1. features ? adoption of risc architecture basic instruction: 1 instruction per cycle ? general-purpose registers: 32-bit 16 registers ? 4 gbytes linear memory space ? multiplier installed 32-bit 32-bit multiplication: 5 cycles 16-bit 16-bit multiplication: 3 cycles ? enhanced interrupt processing function quick response speed (6 cycles) multiple-interrupt support level mask function (16 levels) ? enhanced instructions for i/o operation memory-to-memory transfer instruction bit processing instruction basic instruction word length: 16 bits ? low-power consumption sleep mode/stop mode 2. internal architecture ? the fr family cpu uses the harvard architecture in which the instruction bus and data bus are independent of each other. ?a 32-bit ? 16-bit buffer is connected to the 32-bit bus (d-bus) to provide an interface between the cpu and peripheral resources. ? a harvard ? princeton bus converter is connected to both the i-bus and d-bus to provide an interface between the cpu and the bus controller.
mb91460h series 30 ds07-16616-1e 3. programming model 3.1. basic programming model ilm s cr ccr fp sp ac . . . . . . . . . . . . xxxx xxxx h 0000 0000 h xxxx xxxx h . . . . . . . . . r0 r1 r12 r13 r14 r15 pc ps rp tbr ssp usp mdl mdh . . . . . . 32 bits initial value general-purpose registers program counter program status table base register return pointer system stack pointer user stack pointer multiply & divide registers
mb91460h series ds07-16616-1e 31 4. registers 4.1. general-purpose register registers r0 to r15 are general-purpose registers. these registers can be used as accumulators for computation operations and as pointers for memory access. of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications. r13 : virtual accumulator r14 : frame pointer r15 : stack pointer initial values at reset are undefined for r0 to r14. the value for r15 is 00000000 h (ssp value). 4.2. ps (program status) this register holds the program status, and is divided into three parts, ilm, scr, and ccr. all undefined bits (-) in the diagram are reserved bits. the read values are always ?0?. write access to these bits is invalid. fp sp ac . . . . . . . . . . . . xxxx xxxx h 0000 0000 h xxxx xxxx h . . . . . . . . . r0 r1 r12 r13 r14 r15 . . . . . . 32 bits initial value bit position it 20 bit 0 bit 7 bit 8bit 10 bit 16 ilm scr ccr bit 31
mb91460h series 32 ds07-16616-1e 4.3. ccr (condition code register) sv : supervisor flag s : stack flag i : interrupt enable flag n : negative enable flag z : zero flag v : overflow flag c : carry flag 4.4. scr (system condition register) flag for step division (d1, d0) this flag stores interim data during execution of step division. step trace trap flag (t) this flag indicates whether the step trace trap is enabled or disabled. the step trace trap function is used by emulators. when an emulator is in use, it cannot be used in execution of user programs. 4.5. ilm (interrupt level mask register) this register stores interrupt level mask values, and the values stored in ilm4 to ilm0 are used for level masking. the register is initialized to value ?01111 b ? at reset. 4.6. pc (program counter) the program counter indicates the address of the instruction that is being executed. the initial value at reset is undefined. - 000xxxx b bit 0bit 1bit 2bit 3bit 4bit 5bit 6bit 7 cvznis sv initial value bit 10 bit 8 bit 9 d1 d0 t xx0 b initial value bit 18b it 16 bit 17 ilm2 ilm1 ilm0 01111 b ilm3 ilm4 bit 20 bit 19 initial value bit 0 bit 31 xxxxxxxx h initial value
mb91460h series ds07-16616-1e 33 4.7. tbr (table base register) the table base register stores the starting addre ss of the vector table used in eit processing. the initial value at reset is 000ffc00 h . 4.8. rp (return pointer) the return pointer stores the address for return from subroutines. during execution of a call instruction, the pc value is transferred to this rp register. during execution of a ret instruction, the contents of the rp register are transferred to pc. the initial value at reset is undefined. 4.9. usp (user stack pointer) the user stack pointer, when the s flag is ?1?, this register functions as the r15 register. ? the usp register can also be explicitly specified. the initial value at reset is undefined. ? this register cannot be used with reti instructions. 4.10. multiply & divide registers these registers are for multiplication and division, and are each 32 bits in length. the initial value at reset is undefined. bit 0 bit 31 000ffc00 h initial value bit 0 bit 31 xxxxxxxx h initial value bit 0 bit 31 xxxxxxxx h initial value bit 0 mdl bit 31 mdh
mb91460h series 34 ds07-16616-1e embedded program/da ta memory (flash) 1. flash features ? MB91F464HB : 416 kbytes (6 64 kbytes + 4 8 kbytes = 3.25 mbits) ? programmable wait states for read/write access ? flash and boot security with security vector at 0x0014:8000 - 0x0014:800f ? boot security ? basic specification: same as mbm29lv400tc (except size and part of sector configuration) 2. operation modes: (1) 32-bit cpu mode: ? cpu reads and executes programs in word (32-bit) length units. ? actual flash memory access is performed in word (32-bit) length units. (2) 16-bit cpu mode: ? cpu reads and writes in half-word (16-bit) length units. ? program execution from the flash is not possible. ? actual flash memory access is performed in word (16-bit) length units. (3) flash memory mode (external access to flash memory enabled) note: the operation mode of the flash memory can be selected using a boot-rom function. the function start address is 0xbf60. the parameter description is given in the hardware manual in chapter 54.6 "flash access mode switching".
mb91460h series ds07-16616-1e 35 3. flash access in cpu mode 3.1. flash configuration 3.1.1. flash memory map MB91F464HB roms7 addr+3 addr+4 0009:ffffh 0008:0000h 0007:ffffh 0006:0000h 0005:ffffh 0004:0000h sa12 (64kb) sa13 (64kb) 0014:7fffh 0014:4000h 0014:3fffh 0014:0000h sa15 (64kb) 000d:ffffh 000c:0000h 000b:ffffh 000a:0000h sa17 (64kb) sa14 (64kb) sa22 (64kb) sa20 (64kb) 0013:ffffh 0012:0000h 0011:ffffh 0010:0000h sa18 (64kb) 000f:ffffh 000e:0000h sa7 (8kb) sa5 (8kb) sa3 (8kb) sa1 (8kb) sa23 (64kb) sa6 (8kb) sa4 (8kb) sa2 (8kb) address 0014:ffffh 0014:c000h 0014:bfffh 0014:8000h addr+7 addr+2 sa0 (8kb) sa16 (64kb) sa10 (64kb) sa21 (64kb) sa19 (64kb) dat[15:0] 16bit read/write 32bit read legend memory not available in this area roms2 dat[31:16] dat[15:0] dat[31:0] dat[31:0] dat[31:16] roms1 roms0 addr+6 roms5 roms4 roms6 roms3 memory available in this area addr+5 sa11 (64kb) sa8 (64kb) sa9 (64kb) addr+0 addr+1
mb91460h series 36 ds07-16616-1e 3.2. flash access timing settings in cpu mode the following tables list all settings for a given maximum core frequency (through the setting of clkb or maximum clock modulation) for flash read and write access. 3.2.1. flash read timing settings (synchronous read) 3.2.2. flash write timing settings (synchronous write) core clock (clkb) atd aleh eq wexh wtc remark to 24 mhz 0 0 0 - 1 to 48 mhz 0 0 1 - 2 to 96 mhz 1 1 3 - 4 to 100 mhz 1 1 3 - 4 core clock (clkb) atd aleh eq wexh wtc remark to 16 mhz 0 - - 0 3 to 32 mhz 0 - - 0 4 to 48 mhz 0 - - 0 5 to 64 mhz 1 - - 0 6 to 96 mhz 1 - - 0 7 to 100 mhz 1 - - 0 7
mb91460h series ds07-16616-1e 37 3.3. address mapping from cpu to parallel programming mode the following tables show the calcul ation from cpu addresses to flash macro addresses which are used in parallel programming. 3.3.1. address mapping MB91F464HB note: fa result is without 20:0000h offset for parallel flash programming. set offset by keeping fa[21] = 1 as described in section ?parallel flash programming mode ?. cpu address (addr) condition flash sectors fa (flash address) calculation 14:8000h to 14:ffffh addr[2]==0 sa4, sa6 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 0d:0000h 14:8000h to 14:ffffh addr[2]==1 sa5, sa7 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (addr/2)%4 + addr%4 - 0d:0000h 0a:0000h to 0f:ffffh addr[2]==0 sa14, sa16, sa18 (64 kbyte) fa := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 0a:0000h to 0f:ffffh addr[2]==1 sa15, sa17, sa19 (64 kbyte) fa := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (addr/2)%4 + addr%4
mb91460h series 38 ds07-16616-1e 4. parallel flash programming mode 4.1. flash configuration in parallel flash programming mode parallel flash programming mode (md[2:0] = 111): MB91F464HB fa[20:0] sa0 (8kb) fa[1:0]=00 fa[1:0]=10 sa2 (8kb) sa1 (8kb) 0017:9fffh 0017:8000h sa4 (8kb) sa3 (8kb) 0017:dfffh 0017:c000h 0017:bfffh 0017:a000h sa6 (8kb) sa5 (8kb) 0017:ffffh 0017:e000h sa8 (64kb) sa7 (8kb) sa10 (64kb) sa9 (64kb) sa12 (64kb) sa11 (64kb) 001a:ffffh 001a:0000h sa14 (64kb) sa13 (64kb) 001c:ffffh 001c:0000h 001b:ffffh 001b:0000h sa16 (64kb) sa15 (64kb) 001e:ffffh 001e:0000h 001d:ffffh 001d:0000h sa17 (64kb) 001f:ffffh 001f:0000h sa19 (64kb) sa18 (64kb) dq[15:0] dq[15:0] remark: always keep fa[0] = 0 and fa[20] = 1 16bit write mode legend memory available in this area memory not available in this area
mb91460h series ds07-16616-1e 39 4.2. pin connections in parallel programming mode resetting after setting the md [2:0] pins to [111] will halt cpu functioning. at this time, the flash memory's interface circuit enables direct control of the flash memory unit from external pins by directly linking some of the signals to gp-ports. please see table below for signal mapping. in this mode, the flash memory appears to the external pins as a stand-alone unit. this mode is generally set when writing/erasing using the parallel flash programmer. in this mode, all operations of the 8.5 mbits flash memory's auto algorithms are available. correspondence between mbm29lv400tc and flash memory control signals mbm29lv400tc external pins fr-cpu mode MB91F464HB external pins comment flash memory mode normal function pin number -initx-initx84 reset - frstx gp16_6 70 - - md2 md2 76 set to ?1? - - md1 md1 75 set to ?1? - - md0 md0 74 set to ?1? ry/by fmcs:rdy bit ry/byx gp18_2 100 byte internally fixed to ?h? bytex gp16_4 68 we internal control sig- nal + control via inter- face circuit wex gp16_7 71 oe oex gp07_7 3 ce cex gp07_6 2 - atdin gp18_6 103 set to ?0? - eqin gp18_5 102 set to ?0? - testx gp16_5 69 set to ?1? - rdyi gp18_4 101 set to ?0? a-1 internal address bus fa0 gp05_5 17 set to ?0? a0 to a3 fa1 to fa4 gp19_0 to gp19_2, gp19_4 92 to 95 a4 to a7 fa5 to fa8 gp19_5 to gp19_6, gp18_0 to gp18_1 96 to 99 a8 to a11 fa9 to fa12 gp06_0 to gp06_3 4 to 7 a12 to a15 fa13 to fa16 gp06_4 to gp06_7 8 to 11 a16 to a18 fa17 to fa19 gp05_0 to gp05_2 12 to 14 a19 fa20 gp05_3 15 set to ?1? dq0 to dq7 internal data bus dq0 to dq7 gp00_0 to gp00_7 28 to 35 dq8 to dq15 dq8 to dq15 gp01_0 to gp01_7 20 to 27
mb91460h series 40 ds07-16616-1e 5. poweron sequence in parallel programming mode the flash memory can be accessed in programming mode after a certain wait time, which is needed for security vector fetch: ? minimum wait time after vdd5/vdd5r power on: 2.76 ms ? minimum wait time after initx rising: 1.0 ms 6. flash security 6.1. vector addresses two flash security vectors (fsv1, fsv2) are located parallel to the boot security vectors (bsv1, bsv2) controlling the protecti on functions of the fl ash security module: fsv1: 0x14:8000 bsv1: 0x14:8004 fsv2: 0x14:8008 bsv2: 0x14:800c 6.2. security vector fsv1 the setting of the flash security vector fsv1 is responsible for the read and write protection modes and the individual write protection of the 8 kbytes sectors. 6.2.1. fsv1 (bit31 to bit16) the setting of the flash security vector fsv1 bits [31:16 ] is responsible for the read and write protection modes. explanation of the bits in the flash security vector fsv1[31:16] fsv1[31:19] fsv1[18] write protection level fsv1[17] write protection fsv1[16] read protection flash security mode set all to ?0? set to ?0? set to ?0? set to ?1? read protection (all device modes, ex- cept intvec mode md[2:0]=?000?) set all to ?0? set to ?0? set to ?1? set to ?0? write protection (all device modes, with- out exception) set all to ?0? set to ?0? set to ?1? set to ?1? read protection (all device modes, ex- cept intvec mode md[2:0]=?000?) and write protection (all device modes) set all to ?0? set to ?1? set to ?0? set to ?1? read protection (all device modes, ex- cept intvec mode md[2:0]=?000?) set all to ?0? set to ?1? set to ?1? set to ?0? write protection (all device modes, ex- cept intvec mode md[2:0]=?000?) set all to ?0? set to ?1? set to ?1? set to ?1? read protection (all device modes, ex- cept intvec mode md[2:0]=?000?) and write protection (all device modes except intvec mode md[2:0]=?000?)
mb91460h series ds07-16616-1e 41 6.2.2. fsv1 (bit15 to bit0) MB91F464HB the setting of the flash security vector fsv1 bits [15:0] is responsible for the individual write protection of the 8 kbytes sectors. it is only evaluated if write protection bit fsv1[17] is set. explanation of the bits in the flash security vector fsv1[15:0] note: it is mandatory to always set the sector where the flash security vectors fsv1 and fsv2 are located to write protected (here sector sa4). otherwise it is possible to overwrite the security vector to a setting where it is possible to either read out the flash content or manipulate data by writing. see section ? flash access in cpu mode? for an overview about the sector organisation of the flash memory. fsv1 bit sector enable write protection disable write protection comment fsv1[3:0] ??? not available fsv1[4] sa4 set to ?0? ? write protection is mandatory! fsv1[5] sa5 set to ?0? set to ?1? fsv1[6] sa6 set to ?0? set to ?1? fsv1[7] sa7 set to ?0? set to ?1? fsv1[15:8] ?? ? not available
mb91460h series 42 ds07-16616-1e 6.3. security vector fsv2 MB91F464HB the setting of the flash security vector fsv2 bits [31:0] is responsible for the individual write protection of the 64 kbyte sectors. it is only evaluated if write protection bit fsv1[17] is set. explanation of the bits in the flash security vector fsv2[31:0] note : see section ? flash access in cpu mode? for an overview about the sector organisation of the flash memory. fsv2 bit sector enable write protection disable write protection comment fsv2[5:0] ??? not available fsv2[6] sa14 set to ?0? set to ?1? fsv2[7] sa15 set to ?0? set to ?1? fsv2[8] sa16 set to ?0? set to ?1? fsv2[9] sa17 set to ?0? set to ?1? fsv2[10] sa18 set to ?0? set to ?1? fsv2[11] sa19 set to ?0? set to ?1? fsv2[31:12] ??? not available
mb91460h series ds07-16616-1e 43 memory space the fr family has 4 gbytes of logical address space (2 32 addresses) available to the cpu by linear access. ? direct addressing area the following address space area is used for i/o. this area is called direct addressing area, and the add ress of an operand can be specified directly in an instruction. the size of directly addressable area depends on the length of the data being accessed as shown below. byte data access : 000 h to 0ff h half word access : 000 h to 1ff h word data access : 000 h to 3ff h
mb91460h series 44 ds07-16616-1e memory maps 1. MB91F464HB MB91F464HB 00000000 h 00000400 h i/o (direct addressing area) i/o 00002000 h 00004000 h flash-cache (8 kbytes) 00001000 h dma 00006000 h 00007000 h flash memory control 00008000 h 0000b000 h boot rom (4 kbytes) 0000c000 h can 0000d000 h 0002c000 h d-ram (0 wait, 16 kbytes) 00030000 h id-ram (16 kbytes) 00034000 h 00040000 h flash memory (384 kbytes) 00150000 h 00180000 h external bus area 00500000 h external data bus ffffffff h note: access prohibited areas 00148000 h flash memory (32 kbytes) 00100000 h external bus area 00080000 h external bus area 000a0000 h
mb91460h series ds07-16616-1e 45 i/o map 1. MB91F464HB note : initial values of register bits are represented as follows: ? 1 ? : initial value ? 1 ? ? 0 ? : initial value ? 0 ? ? x ? : initial value ? undefined ? ? - ? : no physical register at this location access is barred with an undefined data access attribute. address register block + 0 + 1 + 2 + 3 000000 h pdr0 [r/w] xxxxxxxx pdr1 [r/w] xxxxxxxx pdr2 [r/w] xxxxxxxx pdr3 [r/w] xxxxxxxx t-unit port data register read/write attribute register initial value after reset register name (column 1 register at address 4n, column 2 register at address 4n + 1...) leftmost register address (for word access, the register in column 1 becomes the msb side of the data.)
mb91460h series 46 ds07-16616-1e address register block +0 +1 +2 +3 000000 h pdr00 [r/w] xxxxxxxx pdr01 [r/w] xxxxxxxx reserved reserved r-bus port data register 000004 h reserved pdr05 [r/w] - - xxxxxx pdr06 [r/w] xxxxxxxx pdr07 [r/w] xxxxxxxx 000008 h pdr08 [r/w] x - - x - - - x pdr09 [r/w] - - - - - - xx pdr10 [r/w] - - - - - - - x reserved 00000c h reserved reserved pdr14 [r/w] xxxxxxxx pdr15 [r/w] xxxxxxxx 000010 h pdr16 [r/w] xxxxxxxx pdr17 [r/w] xxxxxxxx pdr18 [r/w] - xxx - xxx pdr19 [r/w] - xxx - xxx 000014 h pdr20 [r/w] - xxx - xxx pdr21 [r/w] - - - - - - xx pdr22 [r/w] xxxxxxxx pdr23 [r/w] xxxxxxxx 000018 h pdr24 [r/w] xxxxxxxx reserved pdr26 [r/w] xxxxxxxx pdr27 [r/w] xxxxxxxx 00001c h pdr28 [r/w] xxxxxxxx pdr29 [r/w] xxxxxxxx reserved reserved 000020 h to 00002c h reserved 000030 h eirr0 [r/w] xxxxxxxx enir0 [r/w] 00000000 elvr0 [r/w] 00000000 00000000 external interrupt (int 0 to int 7) 000034 h eirr1 [r/w] xxxxxxxx enir1 [r/w] 00000000 elvr1 [r/w] 00000000 00000000 external interrupt (int 8 to int 15) 000038 h dicr [r/w] - - - - - - - 0 hrcl [r/w] 0 - - 11111 rbsync delay interrupt 00003c h reserved reserved 000040 h scr00 [r/w,w] 00000000 smr00 [r/w,w] 00000000 ssr00 [r/w,r] 00001000 rdr00/tdr00 [r/w] 00000000 lin-usart 0 000044 h escr00 [r/w] 00000x00 eccr00 [r/w,r,w] -00000xx reserved 000048 h 00004c h reserved reserved 000050 h scr02 [r/w,w] 00000000 smr02 [r/w,w] 00000000 ssr02 [r/w,r] 00001000 rdr02/tdr02 [r/w] 00000000 lin-usart 2 000054 h escr02 [r/w] 00000x00 eccr02 [r/w,r,w] -00000xx reserved
mb91460h series ds07-16616-1e 47 000058 h scr03 [r/w,w] 00000000 smr03 [r/w,w] 00000000 ssr03 [r/w,r] 00001000 rdr03/tdr03 [r/w] 00000000 lin-usart 3 00005c h escr03 [r/w] 00000x00 eccr03 [r/w,r,w] -00000xx reserved 000060 h scr04 [r/w,w] 00000000 smr04 [r/w,w] 00000000 ssr04 [r/w,r] 00001000 rdr04/tdr04 [r/w] 00000000 lin-usart 4 with fifo 000064 h escr04 [r/w] 00000x00 eccr04 [r/w,r,w] -00000xx fsr04 [r] - - - 00000 fcr04 [r/w] 0001 - 000 000068 h scr05 [r/w,w] 00000000 smr05 [r/w,w] 00000000 ssr05 [r/w,r] 00001000 rdr05/tdr05 [r/w] 00000000 lin-usart 5 with fifo 00006c h escr05 [r/w] 00000x00 eccr05 [r/w,r,w] -00000xx fsr05 [r] - - - 00000 fcr05 [r/w] 0001 - 000 000070 h scr06 [r/w,w] 00000000 smr06 [r/w,w] 00000000 ssr06 [r/w,r] 00001000 rdr06/tdr06 [r/w] 00000000 lin-usart 6 with fifo 000074 h escr06 [r/w] 00000x00 eccr06 [r/w,r,w] -00000xx fsr06 [r] - - - 00000 fcr06 [r/w] 0001 - 000 000078 h scr07 [r/w,w] 00000000 smr07 [r/w,w] 00000000 ssr07 [r/w,r] 00001000 rdr07/tdr07 [r/w] 00000000 lin-usart 7 with fifo 00007c h escr07 [r/w] 00000x00 eccr07 [r/w,r,w] -00000xx fsr07 [r] - - - 00000 fcr07 [r/w] 0001 - 000 000080 h bgr100 [r/w] 00000000 bgr000 [r/w] 00000000 reserved reserved baud rate generator lin-usart 0 to 7 000084 h bgr102 [r/w] 00000000 bgr002 [r/w] 00000000 bgr103 [r/w] 00000000 bgr003 [r/w] 00000000 000088 h bgr104 [r/w] 00000000 bgr004 [r/w] 00000000 bgr105 [r/w] 00000000 bgr005 [r/w] 00000000 00008c h bgr106 [r/w] 00000000 bgr006 [r/w] 00000000 bgr107 [r/w] 00000000 bgr007 [r/w] 00000000 000090 h to 0000cc h reserved reserved address register block +0 +1 +2 +3
mb91460h series 48 ds07-16616-1e 0000d0 h ibcr0 [r/w] 00000000 ibsr0 [r] 00000000 itbah0 [r/w] - - - - - - 00 itbal0 [r/w] 00000000 i 2 c 0 0000d4 h itmkh0 [r/w] 00 - - - - 11 itmkl0 [r/w] 11111111 ismk0 [r/w] 01111111 isba0 [r/w] - 0000000 0000d8 h reserved idar0 [r/w] 00000000 iccr0 [r/w] - 0011111 reserved 0000dc h ibcr1 [r/w] 00000000 ibsr1 [r] 00000000 itbah1 [r/w] - - - - - - 00 itbal1 [r/w] 00000000 i 2 c 1 0000e0 h itmkh1 [r/w] 00 - - - - 11 itmkl1 [r/w] 11111111 ismk1 [r/w] 01111111 isba1 [r/w] - 0000000 0000e4 h reserved idar1 [r/w] 00000000 iccr1 [r/w] - 0011111 reserved 0000e8 h to 0000fc h reserved reserved 000100 h gcn10 [r/w] 00110010 00010000 reserved gcn20 [r/w] - - - - 0000 ppg control 0 to 3 000104 h gcn11 [r/w] 00110010 00010000 reserved gcn21 [r/w] - - - - 0000 ppg control 4 to 7 000108 h gcn12 [r/w] 00110010 00010000 reserved gcn22 [r/w] - - - - 0000 ppg control 8 to 11 000110 h ptmr00 [r] 11111111 11111111 pcsr00 [w] xxxxxxxx xxxxxxxx ppg 0 000114 h pdut00 [w] xxxxxxxx xxxxxxxx pcnh00 [r/w] 0000000 - pcnl00 [r/w] 000000 - 0 000118 h ptmr01 [r] 11111111 11111111 pcsr01 [w] xxxxxxxx xxxxxxxx ppg 1 00011c h pdut01 [w] xxxxxxxx xxxxxxxx pcnh01 [r/w] 0000000 - pcnl01 [r/w] 000000 - 0 000120 h ptmr02 [r] 11111111 11111111 pcsr02 [w] xxxxxxxx xxxxxxxx ppg 2 000124 h pdut02 [w] xxxxxxxx xxxxxxxx pcnh02 [r/w] 0000000 - pcnl02 [r/w] 000000 - 0 000128 h ptmr03 [r] 11111111 11111111 pcsr03 [w] xxxxxxxx xxxxxxxx ppg 3 00012c h pdut03 [w] xxxxxxxx xxxxxxxx pcnh03 [r/w] 0000000 - pcnl03 [r/w] 000000 - 0 000130 h ptmr04 [r] 11111111 11111111 pcsr04 [w] xxxxxxxx xxxxxxxx ppg 4 000134 h pdut04 [w] xxxxxxxx xxxxxxxx pcnh04 [r/w] 0000000 - pcnl04 [r/w] 000000 - 0 address register block +0 +1 +2 +3
mb91460h series ds07-16616-1e 49 000138 h ptmr05 [r] 11111111 11111111 pcsr05 [w] xxxxxxxx xxxxxxxx ppg 5 00013c h pdut05 [w] xxxxxxxx xxxxxxxx pcnh05 [r/w] 0000000 - pcnl05 [r/w] 000000 - 0 000140 h ptmr06 [r] 11111111 11111111 pcsr06 [w] xxxxxxxx xxxxxxxx ppg 6 000144 h pdut06 [w] xxxxxxxx xxxxxxxx pcnh06 [r/w] 0000000 - pcnl06 [r/w] 000000 - 0 000148 h ptmr07 [r] 11111111 11111111 pcsr07 [w] xxxxxxxx xxxxxxxx ppg 7 00014c h pdut07 [w] xxxxxxxx xxxxxxxx pcnh07 [r/w] 0000000 - pcnl07 [r/w] 000000 - 0 000150 h ptmr08 [r] 11111111 11111111 pcsr08 [w] xxxxxxxx xxxxxxxx ppg 8 000154 h pdut08 [w] xxxxxxxx xxxxxxxx pcnh08 [r/w] 0000000 - pcnl08 [r/w] 000000 - 0 000158 h ptmr09 [r] 11111111 11111111 pcsr09 [w] xxxxxxxx xxxxxxxx ppg 9 00015c h pdut09 [w] xxxxxxxx xxxxxxxx pcnh09 [r/w] 0000000 - pcnl09 [r/w] 000000 - 0 000160 h ptmr10 [r] 11111111 11111111 pcsr10 [w] xxxxxxxx xxxxxxxx ppg 10 000164 h pdut10 [w] xxxxxxxx xxxxxxxx pcnh10 [r/w] 0000000 - pcnl10 [r/w] 000000 - 0 000168 h ptmr11 [r] 11111111 11111111 pcsr11 [w] xxxxxxxx xxxxxxxx ppg 11 00016c h pdut11 [w] xxxxxxxx xxxxxxxx pcnh11 [r/w] 0000000 - pcnl11 [r/w] 000000 - 0 000170 h to 00017c h reserved reserved 000180 h reserved ics01 [r/w] 00000000 reserved ics23 [r/w] 00000000 input capture 0 to 3 000184 h ipcp0 [r] xxxxxxxx xxxxxxxx ipcp1 [r] xxxxxxxx xxxxxxxx 000188 h ipcp2 [r] xxxxxxxx xxxxxxxx ipcp3 [r] xxxxxxxx xxxxxxxx address register block +0 +1 +2 +3
mb91460h series 50 ds07-16616-1e 00018c h ocs01 [r/w] - - - 0 - - 00 0000 - - 00 ocs23 [r/w] - - - 0 - - 00 0000 - - 00 output compare 0 to 3 000190 h occp0 [r/w] xxxxxxxx xxxxxxxx occp1 [r/w] xxxxxxxx xxxxxxxx 000194 h occp2 [r/w] xxxxxxxx xxxxxxxx occp3 [r/w] xxxxxxxx xxxxxxxx 000198 h sgcrh [r/w] 0000 - - 00 sgcrl [r/w] - - 0 - - 000 sgfr [r/w, r] xxxxxxxx xxxxxxxx sound generator 00019c h sgar [r/w] 00000000 reserved sgtr [r/w] xxxxxxxx sgdr [r/w] xxxxxxxx 0001a0 h aderh [r/w] 00000000 00000000 aderl [r/w] 00000000 00000000 a/d converter 0001a4 adcs1 [r/w] 00000000 adcs0 [r/w] 00000000 adcr1 [r] 000000xx adcr0 [r] xxxxxxxx 0001a8 h adct1 [r/w] 00010000 adct0 [r/w] 00101100 adsch [r/w] - - - 00000 adech [r/w] - - - 00000 0001ac h reserved acsr0 [r/w] -11xxx00 reserved reserved alarm comparator 0 to 1 0001b0 h tmrlr0 [w] xxxxxxxx xxxxxxxx tmr0 [r] xxxxxxxx xxxxxxxx reload timer 0 (ppg 0, ppg 1) 0001b4 h reserved tmcsrh0 [r/w] - - - 00000 tmcsrl0 [r/w] 0 - 000000 0001b8 h tmrlr1 [w] xxxxxxxx xxxxxxxx tmr1 [r] xxxxxxxx xxxxxxxx reload timer 1 (ppg 2, ppg 3) 0001bc h reserved tmcsrh1 [r/w] - - - 00000 tmcsrl1 [r/w] 0 - 000000 0001c0 h tmrlr2 [w] xxxxxxxx xxxxxxxx tmr2 [r] xxxxxxxx xxxxxxxx reload timer 2 (ppg 4, ppg 5) 0001c4 h reserved tmcsrh2 [r/w] - - - 00000 tmcsrl2 [r/w] 0 - 000000 0001c8 h tmrlr3 [w] xxxxxxxx xxxxxxxx tmr3 [r] xxxxxxxx xxxxxxxx reload timer 3 (ppg 6, ppg 7) 0001cc h reserved tmcsrh3 [r/w] - - - 00000 tmcsrl3 [r/w] 0 - 000000 0001d0 h tmrlr4 [w] xxxxxxxx xxxxxxxx tmr4 [r] xxxxxxxx xxxxxxxx reload timer 4 (ppg 8, ppg 9) 0001d4 h reserved tmcsrh4 [r/w] - - - 00000 tmcsrl4 [r/w] 0 - 000000 address register block +0 +1 +2 +3
mb91460h series ds07-16616-1e 51 0001d8 h tmrlr5 [w] xxxxxxxx xxxxxxxx tmr5 [r] xxxxxxxx xxxxxxxx reload timer 5 (ppg 10, ppg 11) 0001dc h reserved tmcsrh5 [r/w] - - - 00000 tmcsrl5 [r/w] 0 - 000000 0001e0 h tmrlr6 [w] xxxxxxxx xxxxxxxx tmr6 [r] xxxxxxxx xxxxxxxx reload timer 6 (ppg 12, ppg 13) 0001e4 h reserved tmcsrh6 [r/w] - - - 00000 tmcsrl6 [r/w] 0 - 000000 0001e8 h tmrlr7 [w] xxxxxxxx xxxxxxxx tmr7 [r] xxxxxxxx xxxxxxxx reload timer 7 (ppg 14, ppg 15) (a/d converter) 0001ec h reserved tmcsrh7 [r/w] - - - 00000 tmcsrl7 [r/w] 0 - 000000 0001f0 h tcdt0 [r/w] xxxxxxxx xxxxxxxx reserved tccs0 [r/w] 00000000 free running timer 0 (icu 0, icu 1) 0001f4 h tcdt1 [r/w] xxxxxxxx xxxxxxxx reserved tccs1 [r/w] 00000000 free running timer 1 (icu 2, icu 3) 0001f8 h tcdt2 [r/w] xxxxxxxx xxxxxxxx reserved tccs2 [r/w] 00000000 free running timer 2 (ocu 0, ocu 1) 0001fc h tcdt3 [r/w] xxxxxxxx xxxxxxxx reserved tccs3 [r/w] 00000000 free running timer 3 (ocu 2, ocu 3) 000200 h dmaca0 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb0 [r/w] 00000000 0000 0000 xxxxxxxx xxxxxxxx 000208 h dmaca1 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00020c h dmacb1 [r/w] 00000000 0000 0000 xxxxxxxx xxxxxxxx 000210 h dmaca2 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000214 h dmacb2 [r/w] 00000000 0000 0000 xxxxxxxx xxxxxxxx 000218 h dmaca3 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00021c h dmacb3 [r/w] 00000000 0000 0000 xxxxxxxx xxxxxxxx address register block +0 +1 +2 +3
mb91460h series 52 ds07-16616-1e 000220 h dmaca4 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000224 h dmacb4 [r/w] 00000000 0000 0000 xxxxxxxx xxxxxxxx 000228 h to 00023c h reserved 000240 h dmacr [r/w] 00 - - 0000 reserved 000244 h to 0002cc h reserved reserved 0002d0 h reserved ics045 [r/w] 00000000 reserved ics67 [r/w] 00000000 input capture 4 to 7 0002d4 h ipcp4 [r] xxxxxxxx xxxxxxxx ipcp5 [r] xxxxxxxx xxxxxxxx 0002d8 h ipcp6 [r] xxxxxxxx xxxxxxxx ipcp7 [r] xxxxxxxx xxxxxxxx 0002dc h ocs45 [r/w] - - - 0 - - 00 0000 - - 00 ocs67 [r/w] - - - 0 - - 00 0000 - - 00 output compare 4 to 7 0002e0 h occp4 [r/w] xxxxxxxx xxxxxxxx occp5 [r/w] xxxxxxxx xxxxxxxx 0002e4 h occp6 [r/w] xxxxxxxx xxxxxxxx occp7 [r/w] xxxxxxxx xxxxxxxx 0002e8 h to 0002ec h reserved reserved 0002f0 h tcdt4 [r/w] xxxxxxxx xxxxxxxx reserved tccs4 [r/w] 00000000 free running timer 4 (icu 4, icu 5) 0002f4 h tcdt5 [r/w] xxxxxxxx xxxxxxxx reserved tccs5 [r/w] 00000000 free running timer 5 (icu 6, icu 7) 0002f8 h tcdt6 [r/w] xxxxxxxx xxxxxxxx reserved tccs6 [r/w] 00000000 free running timer 6 (ocu 4, ocu 5) 0002fc h tcdt7 [r/w] xxxxxxxx xxxxxxxx reserved tccs7 [r/w] 00000000 free running timer 7 (ocu 6, ocu 7) address register block +0 +1 +2 +3
mb91460h series ds07-16616-1e 53 000300 h udrc1 [w] 00000000 udrc0 [w] 00000000 udcr1 [r] 00000000 udcr0 [r] 00000000 up/down counter 0 to 1 000304 h udcch0 [r/w] 00000000 udccl0 [r/w] 00001000 reserved udcs0 [r/w] 00000000 000308 h udcch1 [r/w] 00000000 udccl1 [r/w] 00001000 reserved udcs1 [r/w] 00000000 00030c h to 00031c h reserved reserved 000320 h gcn13 [r/w] 00110010 00010000 reserved gcn23 [r/w] - - - - 0000 ppg control 12 to 15 000324 h to 00032c h reserved reserved 000330 h ptmr12 [r] 11111111 11111111 pcsr12 [w] xxxxxxxx xxxxxxxx ppg 12 000334 h pdut12 [w] xxxxxxxx xxxxxxxx pcnh12 [r/w] 0000000 - pcnl12 [r/w] 000000 - 0 000338 h ptmr13 [r] 11111111 11111111 pcsr13 [w] xxxxxxxx xxxxxxxx ppg 13 00033c h pdut13 [w] xxxxxxxx xxxxxxxx pcnh13 [r/w] 0000000 - pcnl13 [r/w] 000000 - 0 000340 h ptmr14 [r] 11111111 11111111 pcsr14 [w] xxxxxxxx xxxxxxxx ppg 14 000344 h pdut14 [w] xxxxxxxx xxxxxxxx pcnh14 [r/w] 0000000 - pcnl14 [r/w] 000000 - 0 000348 h ptmr15 [r] 11111111 11111111 pcsr15 [w] xxxxxxxx xxxxxxxx ppg 15 00034c h pdut15 [w] xxxxxxxx xxxxxxxx pcnh15 [r/w] 0000000 - pcnl15 [r/w] 000000 - 0 000350 h to 00038c h reserved reserved 000390 h roms [r] 11111111 01000011 reserved rom select register 000394 h to 0003ec h reserved reserved address register block +0 +1 +2 +3
mb91460h series 54 ds07-16616-1e 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h to 00043c h reserved 000440 h icr00 [r/w] ---11111 icr01 [r/w] ---11111 icr02 [r/w] ---11111 icr03 [r/w] ---11111 interrupt controller 000444 h icr04 [r/w] ---11111 icr05 [r/w] ---11111 icr06 [r/w] ---11111 icr07 [r/w] ---11111 000448 h icr08 [r/w] ---11111 icr09 [r/w] ---11111 icr10 [r/w] ---11111 icr11 [r/w] ---11111 00044c h icr12 [r/w] ---11111 icr13 [r/w] ---11111 icr14 [r/w] ---11111 icr15 [r/w] ---11111 000450 h icr16 [r/w] ---11111 icr17 [r/w] ---11111 icr18 [r/w] ---11111 icr19 [r/w] ---11111 000454 h icr20 [r/w] ---11111 icr21 [r/w] ---11111 icr22 [r/w] ---11111 icr23 [r/w] ---11111 000458 h icr24 [r/w] ---11111 icr25 [r/w] ---11111 icr26 [r/w] ---11111 icr27 [r/w] ---11111 00045c h icr28 [r/w] ---11111 icr29 [r/w] ---11111 icr30 [r/w] ---11111 icr31 [r/w] ---11111 000460 h icr32 [r/w] ---11111 icr33 [r/w] ---11111 icr34[r/w] ---11111 icr35 [r/w] ---11111 000464 h icr36 [r/w] ---11111 icr37 [r/w] ---11111 icr38 [r/w] ---11111 icr39 [r/w] ---11111 000468 h icr40 [r/w] ---11111 icr41 [r/w] ---11111 icr42 [r/w] ---11111 icr43 [r/w] ---11111 00046c h icr44 [r/w] ---11111 icr45 [r/w] ---11111 icr46 [r/w] ---11111 icr47 [r/w] ---11111 000470 h icr48 [r/w] ---11111 icr49 [r/w] ---11111 icr50 [r/w] ---11111 icr51 [r/w] ---11111 000474 h icr52 [r/w] ---11111 icr53 [r/w] ---11111 icr54 [r/w] ---11111 icr55 [r/w] ---11111 000478 h icr56 [r/w] ---11111 icr57 [r/w] ---11111 icr58 [r/w] ---11111 icr59 [r/w] ---11111 address register block +0 +1 +2 +3
mb91460h series ds07-16616-1e 55 00047c h icr60 [r/w] ---11111 icr61 [r/w] ---11111 icr62 [r/w] ---11111 icr63 [r/w] ---11111 interrupt controller 000480 h rsrr [r/w] 10000000 stcr [r/w] 00110011 tbcr [r/w] 00xxxx00 ctbr [w] xxxxxxxx clock control 000484 h clkr [r/w] - - - - 0000 wpr [w] xxxxxxxx divr0 [r/w] 00000011 divr1 [r/w] 00000000 000488 h reserved reserved 00048c h plldivm [r/w] - - - - 0000 plldivn [r/w] - - 000000 plldivg [r/w] - - - - 0000 pllmulg [r/w] 00000000 pll interface 000490 h pllctrl [r/w] - - - - 0000 reserved 000494 h oscc1 [r/w] - - - - - 010 oscs1 [r/w] 00001111 oscc2 [r/w] - - - - - 010 oscs2 [r/w] 00001111 main/sub oscillator control (reserved) 000498 h porten [r/w] - - - - - - 00 reserved port input enable control 0004a0 h reserved wtcer [r/w] - - - - - - 00 wtcr [r/w] 00000000 000 - 00 - 0 real time clock (watch timer) 0004a4 h reserved wtbr [r/w] - - - xxxxx xxxxxxxx xxxxxxxx 0004a8 h wthr [r/w] - - - 00000 wtmr [r/w] - - 000000 wtsr [r/w] - - 000000 reserved 0004ac h csvtr [r/w] - - - 00010 csvcr [r/w] - 011100 cscfg [r/w] 0x000000 cmcfg [r/w] 00000000 clock- supervisor /selector/ monitor 0004b0 h cucr [r/w] - - - - - - - - - - - 0 - - 00 cutd [r/w] 10000000 00000000 calibration of sub clock 0004b4 h cutr1 [r] - - - - - - - - 00000000 cutr2 [r] 00000000 00000000 0004b8 h cmpr [r/w] - - 000010 11111101 reserved cmcr [r/w] - 001 - - 00 clock modulator 0004bc h cmt1 [r/w] 00000000 1 - - - 0000 cmt2 [r/w] - - 000000 - - 000000 0004c0 h canpre [r/w] 0 - - - 0000 canckd [r/w] - - 000000 reserved can clock control 0004c4 h lvsel [r/w] 00000111 lvdet [r/w] 00000 - 00 hwwde [r/w] - - - - - - 00 hwwd [r/w,w] 00011000 low voltage detection/ hardware watchdog 0004c8 h oscrh [r/w] 000 - - 001 oscrl [r/w] - - - - - 000 wpcrh [r/w] 000 - - 001 wpcrl [r/w] - - - - - - 00 main-/sub-oscilla- tion stabilisation timer address register block +0 +1 +2 +3
mb91460h series 56 ds07-16616-1e 0004cc h osccr [r/w] - - - - - - 00 reserved regsel [r/w] - - 000110 regctr [r/w] - - - 0 - - 00 main- oscillation standby control / main/sub regulator control 0004d0 h to 00063c h reserved reserved 000640 h asr0 [r/w] 00000000 00000000 acr0 [r/w] 1111**00 00000000 *2 external bus unit 000644 h asr1 [r/w] xxxxxxxx xxxxxxxx acr1 [r/w] xxxxxxxx xxxxxxxx 000648 h asr2 [r/w] xxxxxxxx xxxxxxxx acr2 [r/w] xxxxxxxx xxxxxxxx 00064c h asr3 [r/w] xxxxxxxx xxxxxxxx acr3 [r/w] xxxxxxxx xxxxxxxx 000650 h asr4 [r/w] xxxxxxxx xxxxxxxx acr4 [r/w] xxxxxxxx xxxxxxxx 000654 h asr5 [r/w] xxxxxxxx xxxxxxxx acr5 [r/w] xxxxxxxx xxxxxxxx 000658 h asr6 [r/w] xxxxxxxx xxxxxxxx acr6 [r/w] xxxxxxxx xxxxxxxx 00065c h asr7 [r/w] xxxxxxxx xxxxxxxx acr7 [r/w] xxxxxxxx xxxxxxxx 000660 h awr0 [r/w] 01111111 11111*11 awr1 [r/w] xxxxxxxx xxxxxxxx 000664 h awr2 [r/w] xxxxxxxx xxxxxxxx awr3 [r/w] xxxxxxxx xxxxxxxx 000668 h awr4 [r/w] xxxxxxxx xxxxxxxx awr5 [r/w] xxxxxxxx xxxxxxxx 00066c h awr6 [r/w] xxxxxxxx xxxxxxxx awr7 [r/w] xxxxxxxx xxxxxxxx 000670 h mcra [r/w] xxxxxxxx mcrb [r/w] xxxxxxxx reserved 000674 h reserved 000678 h iowr0 [r/w] xxxxxxxx iowr1 [r/w] xxxxxxxx iowr2 [r/w] xxxxxxxx iowr3 [r/w] xxxxxxxx 00067c h reserved 000680 h cser [r/w] 00000001 cher [r/w] 11111111 reserved tcr [r/w] 0000**** *3 000684 h rcrh [r/w] 00xxxxxx rcrl [r/w] xxxx0xxx reserved address register block +0 +1 +2 +3
mb91460h series ds07-16616-1e 57 000688 h to 0007f8 h reserved external bus unit 0007fc h reserved modr [w] xxxxxxxx reserved mode register 000800 h to 000cfc h reserved reserved 000d00 h pdrd00 [r] xxxxxxxx pdrd01 [r] xxxxxxxx reserved r-bus port data direct read register 000d04 h reserved pdrd05 [r] - - xxxxxx pdrd06 [r] xxxxxxxx pdrd07 [r] xxxxxxxx 000d08 h pdrd08 [r] x - - x - - -x pdrd09 [r] - - - - - - xx pdrd10 [r] - - - - - - - x reserved 000d0c h reserved pdrd14 [r] xxxxxxxx pdrd15 [r] xxxxxxxx 000d10 h pdrd16 [r] xxxxxxxx pdrd17 [r] xxxxxxxx pdrd18 [r] - xxx - xxx pdrd19 [r] - xxx - xxx 000d14 h pdrd20 [r] - xxx - xxx pdrd21 [r] - - - - - - - x pdrd22 [r] xxxxxxxx pdrd23 [r] xxxxxxxx 000d18 h pdrd24 [r] xxxxxxxx reserved pdrd26 [r] xxxxxxxx pdrd27 [r] xxxxxxxx 000d1c h pdrd28 [r] xxxxxxxx pdrd29 [r] xxxxxxxx reserved 000d20 h to 000d3c h reserved 000d40 h ddr00 [r/w] 00000000 ddr01 [r/w] 00000000 reserved r-bus port direction register 000d44 h reserved ddr05 [r/w] - - 000000 ddr06 [r/w] 00000000 ddr07 [r/w] 00000000 000d48 h ddr08 [r/w] 0 - - 0 - - -0 ddr09 [r/w] - - - - - - 00 ddr10 [r/w] - - - - - - -0 reserved 000d4c h reserved ddr14 [r/w] 00000000 ddr15 [r/w] 00000000 000d50 h ddr16 [r/w] 00000000 ddr17 [r/w] 00000000 ddr18 [r/w] - 000 - 000 ddr19 [r/w] - 000 - 000 000d54 h ddr20 [r/w] - 000 - 000 ddr21 [r/w] - - - - - - 00 ddr22 [r/w] 00000000 ddr23 [r/w] 00000000 000d58 h ddr24 [r/w] 00000000 reserved ddr26 [r/w] 00000000 ddr27 [r/w] 00000000 000d5c h ddr28 [r/w] 00000000 ddr29 [r/w] 00000000 reserved address register block +0 +1 +2 +3
mb91460h series 58 ds07-16616-1e 000d60 h to 000d7c h reserved reserved 000d80 h pfr00 [r/w] 11111111 pfr01 [r/w] 11111111 reserved r-bus port function register 000d84 h reserved pfr05 [r/w] - - 111111 pfr06 [r/w] 11111111 pfr07 [r/w] 11111111 000d88 h pfr08 [r/w] 1 - - 1 - - 11 pfr09 [r/w] - - - - - - 11 pfr10 [r/w] - - - - - - -1 reserved 000d8c h reserved pfr14 [r/w] 00000000 pfr15 [r/w] 00000000 000d90 h pfr16 [r/w] 00000000 pfr17 [r/w] 00000000 pfr18 [r/w] - 000 - 000 pfr19 [r/w] - 000 - 000 000d94 h pfr20 [r/w] - 000 - 000 pfr21 [r/w] - - - - - - 00 pfr22 [r/w] 0000-0-0 pfr23 [r/w] -0000000 000d98 h pfr24 [r/w] 00000000 reserved pfr26 [r/w] 00000000 pfr27 [r/w] 00000000 000d9c h pfr28 [r/w] 00000000 pfr29 [r/w] 00000000 reserved 000da0 h to 000dc4 h reserved 000dc8 h reserved epfr10 [r/w] - - - - - - - 0 reserved r-bus port extra function register 000dcc h reserved epfr14 [r/w] 00000000 epfr15 [r/w] 00000000 000dd0 h epfr16 [r/w] 0 - 00 - - - - reserved epfr18 [r/w] - 000 - 000 epfr19 [r/w] - 0- - - 0- - 000dd4 h epfr20 [r/w] - 000 - 000 epfr21 [r/w] - - - - - - - - reserved 000dd8 h reserved epfr26 [r/w] 00000000 epfr27 [r/w] 00000000 000ddc h to 000dfc h reserved reserved address register block +0 +1 +2 +3
mb91460h series ds07-16616-1e 59 000e00 h podr00 [r/w] 00000000 podr01 [r/w] 00000000 reserved r-bus port output drive select register 000e04 h reserved podr05 [r/w] - - 000000 podr06 [r/w] 00000000 podr07 [r/w] 00000000 000e08 h podr08 [r/w] 0 - - 0 - - - 0 podr09 [r/w] - - - - - - 00 podr10 [r/w] - - - - - - - 0 reserved 000e0c h reserved podr14 [r/w] 00000000 podr15 [r/w] 00000000 000e10 h podr16 [r/w] 00000000 podr17 [r/w] 00000000 podr18 [r/w] - 000 - 000 podr19 [r/w] - 000 - 000 000e14 h podr20 [r/w] - 000 - 000 podr21 [r/w] - - - - - - 00 podr22 [r/w] 00000000 podr23 [r/w] 00000000 000e18 h podr24 [r/w] 00000000 reserved podr26 [r/w] 00000000 podr27 [r/w] 00000000 000e1c h podr28 [r/w] 00000000 podr29 [r/w] 00000000 reserved 000e20 h to 000e3c h reserved reserved 000e40 h pilr00 [r/w] 00000000 pilr01 [r/w] 00000000 reserved r-bus port input level select register 000e44 h reserved pilr05 [r/w] - - 000000 pilr06 [r/w] 00000000 pilr07 [r/w] 00000000 000e48 h pilr08 [r/w] 0 - - 0 - - - 0 pilr09 [r/w] - - - - - - 00 pilr10 [r/w] - - - - - - - 0 reserved 000e4c h reserved pilr14 [r/w] 00000000 pilr15 [r/w] 00000000 000e50 h pilr16 [r/w] 00000000 pilr17 [r/w] 00000000 pilr18 [r/w] - - - - - 000 pilr19 [r/w] - 000 - 000 000e54 h pilr20 [r/w] - 000 - 000 pilr21 [r/w] - - - - - - 00 pilr22 [r/w] 00000000 pilr23 [r/w] 00000000 000e58 h pilr24 [r/w] 00000000 reserved pilr26 [r/w] 00000000 pilr27 [r/w] 00000000 000e5c h pilr28 [r/w] 00000000 pilr29 [r/w] 00000000 reserved 000e60 h to 000e7c h reserved reserved address register block +0 +1 +2 +3
mb91460h series 60 ds07-16616-1e 000e80 h epilr00 [r/w] 00000000 epilr01 [r/w] 00000000 reserved r-bus port extra input level select register 000e84 h reserved epilr05 [r/w] - - 000000 epilr06 [r/w] 00000000 epilr07 [r/w] 00000000 000e88 h epilr08 [r/w] 0 - - 0- - - 0 epilr09 [r/w] - - - - - - 00 epilr10 [r/w] - - - - - - - 0 reserved 000e8c h reserved epilr14 [r/w] 00000000 epilr15 [r/w] 00000000 000e90 h epilr16 [r/w] 00000000 epilr17 [r/w] 00000000 epilr18 [r/w] - - - - - 000 epilr19 [r/w] - 000 - 000 000e94 h epilr20 [r/w] - 000 - 000 epilr21 [r/w] - - - - - - 00 epilr22 [r/w] 00000000 epilr23 [r/w] 00000000 000e98 h epilr24 [r/w] 00000000 reserved epilr26 [r/w] 00000000 epilr27 [r/w] 00000000 000e9c h epilr28 [r/w] 00000000 epilr29 [r/w] 00000000 reserved 000ea0 h to 000ebc h reserved reserved 000ec0 h pper00 [r/w] 00000000 pper01 [r/w] 00000000 reserved r-bus port pull-up/down enable register 000ec4 h reserved pper05 [r/w] - - 000000 pper06 [r/w] 00000000 pper07 [r/w] 00000000 000ec8 h pper08 [r/w] 0 - - 0 - - - 0 pper09 [r/w] - - - - - - 00 pper10 [r/w] - - - - - - - 0 reserved 000ecc h reserved pper14 [r/w] 00000000 pper15 [r/w] 00000000 000ed0 h pper16 [r/w] 00000000 pper17 [r/w] 00000000 pper18 [r/w] - 000 - 000 pper19 [r/w] - 000 - 000 000ed4 h pper20 [r/w] - 000 - 000 pper21 [r/w] - - - - - - 00 pper22 [r/w] 00000000 pper23 [r/w] 00000000 000ed8 h pper24 [r/w] 00000000 reserved pper26 [r/w] 00000000 pper27 [r/w] 00000000 000edc h pper28 [r/w] 00000000 pper29 [r/w] 00000000 reserved 000ee0 h to 000efc h reserved reserved address register block +0 +1 +2 +3
mb91460h series ds07-16616-1e 61 000f00 h ppcr00 [r/w] 11111111 ppcr01 [r/w] 11111111 reserved r-bus port pull-up/down con- trol register 000f04 h reserved ppcr05 [r/w] - - 111111 ppcr06 [r/w] 11111111 ppcr07 [r/w] 11111111 000f08 h ppcr08 [r/w] 1 - - 1 - - - 1 ppcr09 [r/w] - - - - - - 11 ppcr10 [r/w] - - - - - - - 1 reserved 000f0c h reserved ppcr14 [r/w] 00000000 ppcr15 [r/w] 11111111 000f10 h ppcr16 [r/w] 00000000 ppcr17 [r/w] 00000000 ppcr18 [r/w] - 111- 111 ppcr19 [r/w] - 111- 111 000f14 h ppcr20 [r/w] - 111- 111 ppcr21 [r/w] - - - - - - 11 ppcr22 [r/w] 11111111 ppcr23 [r/w] 11111111 000f18 h ppcr24 [r/w] 11111111 reserved ppcr26 [r/w] 11111111 ppcr27 [r/w] 11111111 000f1c h ppcr28 [r/w] 11111111 ppcr29 [r/w] 11111111 reserved 000f20 h to 000f3c h reserved reserved 001000 h dmasa0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 001004 h dmada0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001008 h dmasa1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00100c h dmada1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001010 h dmasa2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001014 h dmada2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001018 h dmasa3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00101c h dmada3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001020 h dmasa4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001024 h dmada4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001028 h to 003ffc h reserved reserved address register block +0 +1 +2 +3
mb91460h series 62 ds07-16616-1e 002000 h to 006ffc h flash-cache size is 8 kbytes : 004000 h to 005ffc h flash-cache / i-ram area 007000 h fmcs [r/w] 01101000 fmcr [r/w] - - - - 0000 fchcr [r/w] - - - - - - 00 10000011 flash memory/ i-cache control register 007004 h fmwt [r/w] 11111111 11111111 reserved fmps [r/w] - - - - - 000 007008 h fmac [r] 00000000 00000000 00000000 00000000 00700c h fcha0 [r/w] - - - - - - - - - - 000000 00000000 00000000 i-cache non-cache- able area setting register 007010 h fcha1 [r/w] - - - - - - - - - - 000000 00000000 00000000 007014 h to 007ffc h reserved reserved 008000 h to 00bffc h boot-rom size is 4 kbytes : 00b000 h to 00bffc h (instruction access is 1 wait cycl e, data access is 1 wait cycle) boot rom area 00c000 h ctrlr0 [r/w] 00000000 00000001 statr0 [r/w] 00000000 00000000 can 0 control register 00c004 h errcnt0 [r] 00000000 00000000 btr0 [r/w] 00100011 00000001 00c008 h intr0 [r] 00000000 00000000 testr0 [r/w] 00000000 x0000000 00c00c h brpe0 [r/w] 00000000 00000000 cbsync0 address register block +0 +1 +2 +3
mb91460h series ds07-16616-1e 63 00c010 h if1creq0 [r/w] 00000000 00000001 if1cmsk0 [r/w] 00000000 00000000 can 0 if 1 register 00c014 h if1msk20 [r/w] 11111111 11111111 if1msk10 [r/w] 11111111 11111111 00c018 h if1arb20 [r/w] 00000000 00000000 if1arb10 [r/w] 00000000 00000000 00c01c h if1mctr0 [r/w] 00000000 00000000 reserved 00c020 h if1dta10 [r/w] 00000000 00000000 if1dta20 [r/w] 00000000 00000000 00c024 h if1dtb10 [r/w] 00000000 00000000 if1dtb20 [r/w] 00000000 00000000 00c028 h to 00c02c h reserved 00c030 h if1dta20 [r/w] 00000000 00000000 if1dta10 [r/w] 00000000 00000000 00c034 h if1dtb20 [r/w] 00000000 00000000 if1dtb10 [r/w] 00000000 00000000 00c038 h to 00c03c h reserved 00c040 h if2creq0 [r/w] 00000000 00000001 if2cmsk0 [r/w] 00000000 00000000 can 0 if 2 register 00c044 h if2msk20 [r/w] 11111111 11111111 if2msk10 [r/w] 11111111 11111111 00c048 h if2arb20 [r/w] 00000000 00000000 if2arb10 [r/w] 00000000 00000000 address register block +0 +1 +2 +3
mb91460h series 64 ds07-16616-1e 00c04c h if2mctr0 [r/w] 00000000 00000000 reserved 00c050 h if2dta10 [r/w] 00000000 00000000 if2dta20 [r/w] 00000000 00000000 00c054 h if2dtb10 [r/w] 00000000 00000000 if2dtb20 [r/w] 00000000 00000000 00c058 h to 00c05c h reserved 00c060 h if2dta20 [r/w] 00000000 00000000 if2dta10 [r/w] 00000000 00000000 00c064 h if2dtb20 [r/w] 00000000 00000000 if2dtb10 [r/w] 00000000 00000000 00c068 h to 00c07c h reserved 00c080 h treqr20 [r] 00000000 00000000 treqr10 [r] 00000000 00000000 can 0 status flags 00c084 h to 00c08c h reserved reserved 00c090 h newdt20 [r] 00000000 00000000 newdt10 [r] 00000000 00000000 00c094 h to 00c09c h reserved reserved 00c0a0 h intpnd20 [r] 00000000 00000000 intpnd10 [r] 00000000 00000000 00c0a4 h to 00c0ac h reserved reserved 00c0b0 h msgval20 [r] 00000000 00000000 msgval10 [r] 00000000 00000000 00c0b4 h to 00c0fc h reserved reserved 00c100 h to 00effc h reserved reserved address register block +0 +1 +2 +3
mb91460h series ds07-16616-1e 65 address register block +0 +1 +2 +3 00f000 h bctrl [r/w] - - - - - - - - - - - - - - - - 11111100 00000000 edsu / mpu 00f004 h bstat [r/w] - - - - - - - - - - - - - 000 00000000 10 - - 000000 00f008 h biac [r] - - - - - - - - - - - - - - - - 00000000 00000000 00f00c h boac [r] - - - - - - - - - - - - - - - - 00000000 00000000 00f010 h birq [r/w] - - - - - - - - - - - - - - - - 00000000 00000000 00f014 h to 00f01c h reserved 00f020 h bcr0 [r/w] - - - - - - - - 00000000 00000000 00000000 00f024 h bcr1 [r/w] - - - - - - - - 00000000 00000000 00000000 00f028 h bcr2 [r/w] - - - - - - - - 00000000 00000000 00000000 00f02c h bcr3 [r/w] - - - - - - - - 00000000 00000000 00000000 00f030 h to 00f07c h reserved reserved
mb91460h series 66 ds07-16616-1e *1 : depends on the number of available can channels 00f080 h bad0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx edsu / mpu 00f084 h bad1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f088 h bad2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f08c h bad3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f090 h bad4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f094 h bad5 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f098 h bad6 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f09c h bad7 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0a0 h bad8 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0a4 h bad9 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0a8 h bad10 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0ac h bad11 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0b0 h bad12 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0b4 h bad13 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0b8 h bad14 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0bc h bad15 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0c0 h to 01fffc h reserved edsu / mpu 020000 h to 02fffc h d-ram size is 16 kbytes : 02c000 h - 02fffc h (data access is 0 wait cycles) d-ram area 030000 h to 03fffc h id-ram size is 16 kbytes : 030000 h - 033ffc h (instruction access is 0 wait cycles, data access is 1 wait cycle) id-ram area address register block +0 +1 +2 +3
mb91460h series ds07-16616-1e 67 *2 : acr0 [11 : 10] depends on mode vector fetch information on bus width *3 : tcr [3 : 0] init value = 0000, keeps value after rst
mb91460h series 68 ds07-16616-1e 2. flash memory and external bus area 2.1. MB91F464HB (continued) 32bit read dat[31:0] dat[31:0] 16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0] address register block + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 040000 h to 05fff8 h reserved reserved roms0 060000 h to 07fff8 h reserved reserved roms1 080000 h to 09fff8 h reserved reserved roms2 0a0000 h to 0bfff8 h sa14 (64kb) sa15 (64kb) roms3 0c0000 h to 0dfff8 h sa16 (64kb) sa17 (64kb) roms4 0e0000 h to 0ffff0 h sa18 (64kb) sa19 (64kb) roms5 0ffff8 h fmv [r] 06 00 00 00 h frv [r] 00 00 bf f8 h 100000 h to 11fff8 h external bus area roms6 120000 h to 13fff8 h 140000 h to 143ff8 h external bus area roms7 144000 h to 17ff8 h 148000 h to 14bff8 h sa4 (8kb) sa5 (8kb) 14c000 h to 14fff8 h sa6 (8kb) sa7 (8kb) 150000 h to17fff8 h reserved
mb91460h series ds07-16616-1e 69 (continued) note: write operations to address 0ffff8 h and 0ffffc h are not possible. when reading these addresses, the values shown above will be read. 32bit read dat[31:0] dat[31:0] 16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0] address register block + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 180000 h to 1bfff8 h external bus area roms8 1c0000 h to 1ffff8 h roms9 200000 h to 27fff8 h roms10 280000 h to 2ffff8 h roms11 300000 h to 37fff8 h roms12 380000 h to 3ffff8 h roms13 400000 h to 47fff8 h roms14 480000 h to 4ffff8 h roms15
mb91460h series 70 ds07-16616-1e interrupt vector table interrupt interrupt num- ber interrupt level * 1 interrupt vector *2 dma resource number deci- mal hexa- deci- mal setting register register address offset default vec- tor address reset 0 00 ? ? 3fc h 000ffffc h ? mode vector 1 01 ? ? 3f8 h 000ffff8 h ? system reserved 2 02 ? ? 3f4 h 000ffff4 h ? system reserved 3 03 ? ? 3f0 h 000ffff0 h ? system reserved 4 04 ? ? 3ec h 000fffec h ? cpu supervisor mode (int #5 instruction) *5 505 ? ?3e8 h 000fffe8 h ? memory protection exception *5 606 ? ?3e4 h 000fffe4 h ? system reserved 7 07 ? ? 3e0 h 000fffe0 h ? system reserved 8 08 ? ? 3dc h 000fffdc h ? system reserved 9 09 ? ? 3d8 h 000fffd8 h ? system reserved 10 0a ? ? 3d4 h 000fffd4 h ? system reserved 11 0b ? ? 3d0 h 000fffd0 h ? system reserved 12 0c ? ? 3cc h 000fffcc h ? system reserved 13 0d ? ? 3c8 h 000fffc8 h ? undefined instruction exception 14 0e ? ? 3c4 h 000fffc4 h ? nmi request 15 0f f h fixed 3c0 h 000fffc0 h ? external interrupt 0 16 10 icr00 440 h 3bc h 000fffbc h 0, 16 external interrupt 1 17 11 3b8 h 000fffb8 h 1, 17 external interrupt 2 18 12 icr01 441 h 3b4 h 000fffb4 h 2, 18 external interrupt 3 19 13 3b0 h 000fffb0 h 3, 19 external interrupt 4 20 14 icr02 442 h 3ac h 000fffac h 20 external interrupt 5 21 15 3a8 h 000fffa8 h 21 external interrupt 6 22 16 icr03 443 h 3a4 h 000fffa4 h 22 external interrupt 7 23 17 3a0 h 000fffa0 h 23 external interrupt 8 24 18 icr04 444 h 39c h 000fff9c h ? external interrupt 9 25 19 398 h 000fff98 h ? external interrupt 10 26 1a icr05 445 h 394 h 000fff94 h ? external interrupt 11 27 1b 390 h 000fff90 h ? external interrupt 12 28 1c icr06 446 h 38c h 000fff8c h ? external interrupt 13 29 1d 388 h 000fff88 h ? external interrupt 14 30 1e icr07 447 h 384 h 000fff84 h ? external interrupt 15 31 1f 380 h 000fff80 h ?
mb91460h series ds07-16616-1e 71 reload timer 0 32 20 icr08 448 h 37c h 000fff7c h 4, 32 reload timer 1 33 21 378 h 000fff78 h 5, 33 reload timer 2 34 22 icr09 449 h 374 h 000fff74 h 34 reload timer 3 35 23 370 h 000fff70 h 35 reload timer 4 36 24 icr10 44a h 36c h 000fff6c h 36 reload timer 5 37 25 368 h 000fff68 h 37 reload timer 6 38 26 icr11 44b h 364 h 000fff64 h 38 reload timer 7 39 27 360 h 000fff60 h 39 free run timer 0 40 28 icr12 44c h 35c h 000fff5c h 40 free run timer 1 41 29 358 h 000fff58 h 41 free run timer 2 42 2a icr13 44d h 354 h 000fff54 h 42 free run timer 3 43 2b 350 h 000fff50 h 43 free run timer 4 44 2c icr14 44e h 34c h 000fff4c h 44 free run timer 5 45 2d 348 h 000fff48 h 45 free run timer 6 46 2e icr15 44f h 344 h 000fff44 h 46 free run timer 7 47 2f 340 h 000fff40 h 47 can 0 48 30 icr16 450 h 33c h 000fff3c h ? reserved 49 31 338 h 000fff38 h ? reserved 50 32 icr17 451 h 334 h 000fff34 h ? reserved 51 33 330 h 000fff30 h ? reserved 52 34 icr18 452 h 32c h 000fff2c h ? reserved 53 35 328 h 000fff28 h ? lin-usart 0 rx 54 36 icr19 453 h 324 h 000fff24 h 6, 48 lin-usart 0 tx 55 37 320 h 000fff20 h 7, 49 reserved 56 38 icr20 454 h 31c h 000fff1c h 8, 50 reserved 57 39 318 h 000fff18 h 9, 51 lin-usart 2 rx 58 3a icr21 455 h 314 h 000fff14 h 52 lin-usart 2 tx 59 3b 310 h 000fff10 h 53 lin-usart 3 rx 60 3c icr22 456 h 30c h 000fff0c h 54 lin-usart 3 tx 61 3d 308 h 000fff08 h 55 system reserved 62 3e icr23 *3 457 h 304 h 000fff04 h ? delayed interrupt 63 3f 300 h 000fff00 h ? system reserved *4 64 40 icr24 458 h 2fc h 000ffefc h ? system reserved *4 65 41 2f8 h 000ffef8 h ? interrupt interrupt num- ber interrupt level * 1 interrupt vector *2 dma resource number deci- mal hexa- deci- mal setting register register address offset default vec- tor address
mb91460h series 72 ds07-16616-1e lin-usart (fifo) 4 rx 66 42 icr25 459 h 2f4 h 000ffef4 h 10, 56 lin-usart (fifo) 4 tx 67 43 2f0 h 000ffef0 h 11, 57 lin-usart (fifo) 5 rx 68 44 icr26 45a h 2ec h 000ffeec h 12, 58 lin-usart (fifo) 5 tx 69 45 2e8 h 000ffee8 h 13, 59 lin-usart (fifo) 6 rx 70 46 icr27 45b h 2e4 h 000ffee4 h 60 lin-usart (fifo) 6 tx 71 47 2e0 h 000ffee0 h 61 lin-usart (fifo) 7 rx 72 48 icr28 45c h 2dc h 000ffedc h 62 lin-usart (fifo) 7 tx 73 49 2d8 h 000ffed8 h 63 i 2 c 0 74 4a icr29 45d h 2d4 h 000ffed4 h ? i 2 c 1 75 4b 2d0 h 000ffed0 h ? reserved 76 4c icr30 45e h 2cc h 000ffecc h 64 reserved 77 4d 2c8 h 000ffec8 h 65 reserved 78 4e icr31 45f h 2c4 h 000ffec4 h 66 reserved 79 4f 2c0 h 000ffec0 h 67 reserved 80 50 icr32 460 h 2bc h 000ffebc h 68 reserved 81 51 2b8 h 000ffeb8 h 69 reserved 82 52 icr33 461 h 2b4 h 000ffeb4 h 70 reserved 83 53 2b0 h 000ffeb0 h 71 reserved 84 54 icr34 462 h 2ac h 000ffeac h 72 reserved 85 55 2a8 h 000ffea8 h 73 reserved 86 56 icr35 463 h 2a4 h 000ffea4 h 74 reserved 87 57 2a0 h 000ffea0 h 75 reserved 88 58 icr36 464 h 29c h 000ffe9c h 76 reserved 89 59 298 h 000ffe98 h 77 reserved 90 5a icr37 465 h 294 h 000ffe94 h 78 reserved 91 5b 290 h 000ffe90 h 79 input capture 0 92 5c icr38 466 h 28c h 000ffe8c h 80 input capture 1 93 5d 288 h 000ffe88 h 81 input capture 2 94 5e icr39 467 h 284 h 000ffe84 h 82 input capture 3 95 5f 280 h 000ffe80 h 83 input capture 4 96 60 icr40 468 h 27c h 000ffe7c h 84 input capture 5 97 61 278 h 000ffe78 h 85 input capture 6 98 62 icr41 469 h 274 h 000ffe74 h 86 input capture 7 99 63 270 h 000ffe70 h 87 interrupt interrupt num- ber interrupt level * 1 interrupt vector *2 dma resource number deci- mal hexa- deci- mal setting register register address offset default vec- tor address
mb91460h series ds07-16616-1e 73 output compare 0 100 64 icr42 46a h 26c h 000ffe6c h 88 output compare 1 101 65 268 h 000ffe68 h 89 output compare 2 102 66 icr43 46b h 264 h 000ffe64 h 90 output compare 3 103 67 260 h 000ffe60 h 91 output compare 4 104 68 icr44 46c h 25c h 000ffe5c h 92 output compare 5 105 69 258 h 000ffe58 h 93 output compare 6 106 6a icr45 46d h 254 h 000ffe54 h 94 output compare 7 107 6b 250 h 000ffe50 h 95 sound generator 108 6c icr46 46e h 24c h 000ffe4c h ? reserved 109 6d 248 h 000ffe48 h ? system reserved 110 6e icr47 *3 46f h 244 h 000ffe44 h ? system reserved 111 6f 240 h 000ffe40 h ? ppg 0 112 70 icr48 470 h 23c h 000ffe3c h 15, 96 ppg 1 113 71 238 h 000ffe38 h 97 ppg 2 114 72 icr49 471 h 234 h 000ffe34 h 98 ppg 3 115 73 230 h 000ffe30 h 99 ppg 4 116 74 icr50 472 h 22c h 000ffe2c h 100 ppg 5 117 75 228 h 000ffe28 h 101 ppg 6 118 76 icr51 473 h 224 h 000ffe24 h 102 ppg 7 119 77 220 h 000ffe20 h 103 ppg 8 120 78 icr52 474 h 21c h 000ffe1c h 104 ppg 9 121 79 218 h 000ffe18 h 105 ppg 10 122 7a icr53 475 h 214 h 000ffe14 h 106 ppg 11 123 7b 210 h 000ffe10 h 107 ppg 12 124 7c icr54 476 h 20c h 000ffe0c h 108 ppg 13 125 7d 208 h 000ffe08 h 109 ppg 14 126 7e icr55 477 h 204 h 000ffe04 h 110 ppg 15 127 7f 200 h 000ffe00 h 111 up/down counter 0 128 80 icr56 478 h 1fc h 000ffdfc h ? up/down counter 1 129 81 1f8 h 000ffdf8 h ? reserved 130 82 icr57 479 h 1f4 h 000ffdf4 h ? reserved 131 83 1f0 h 000ffdf0 h ? real time clock 132 84 icr58 47a h 1ec h 000ffdec h ? calibration unit 133 85 1e8 h 000ffde8 h ? interrupt interrupt num- ber interrupt level * 1 interrupt vector *2 dma resource number deci- mal hexa- deci- mal setting register register address offset default vec- tor address
mb91460h series 74 ds07-16616-1e *1 : the interrupt control registers (icrs) are located in the interrupt controller and set the interrupt level for each interrupt request. an icr is provided for each interrupt request. *2 : the vector address for each eit (exception, interrupt or trap) is calculated by addi ng the listed offset to the table base register value (tbr) . the tbr specifies the top of the eit vector table. the addresses listed in the table are for the default tbr value (000ffc00 h ) . the tbr is initialized to this value by a reset. the tbr is set to 000ffc00 h after the internal boot rom is executed. *3 : icr23 and icr47 can be exchanged by se tting the realos compatibility bit (addr 0c03 h : ios[0]) *4 : used by realos *5 : memory protection unit (mpu) support a/d converter 0 134 86 icr59 47b h 1e4 h 000ffde4 h 14, 112 system reserved 135 87 1e0 h 000ffde0 h ? alarm comparator 0 136 88 icr60 47c h 1dc h 000ffddc h ? reserved 137 89 1d8 h 000ffdd8 h ? low voltage detection 138 8a icr61 47d h 1d4 h 000ffdd4 h ? reserved 139 8b 1d0 h 000ffdd0 h ? time base overflow 140 8c icr62 47e h 1cc h 000ffdcc h ? pll clock gear 141 8d 1c8 h 000ffdc8 h ? dma controller 142 8e icr63 47f h 1c4 h 000ffdc4 h ? main/sub osc stability wait 143 8f 1c0 h 000ffdc0 h ? security vector 144 90 ? ? 1bc h 000ffdbc h ? used by the int instruction. 145 to 255 91 to ff ?? 1b8 h to 000 h 000ffdb8 h to 000ffc00 h ? interrupt interrupt num- ber interrupt level * 1 interrupt vector *2 dma resource number deci- mal hexa- deci- mal setting register register address offset default vec- tor address
mb91460h series ds07-16616-1e 75 recommended settings 1. pll and clockgear settings please note that for MB91F464HB the core base clock frequencies are valid in the 1.8v operation mode of the main regulator and flash . recommended pll divider and clockgear settings pll input (clk) [mhz] frequency parameter clockgear parameter pll output (x) [mhz] core base clock [mhz] remarks divm divn divg mulg mulg 4 2 25 16 24 200 100 4 2 24 16 24 192 96 4 2 23 16 24 184 92 4 2 22 16 24 176 88 4 2 21 16 20 168 84 4 2 20 16 20 160 80 4 2 19 16 20 152 76 4 2 18 16 20 144 72 4 2 17 16 16 136 68 4 2 16 16 16 128 64 4 2 15 16 16 120 60 4 2 14 16 16 112 56 4 2 13 16 12 104 52 4 2 12 16 12 96 48 4 2 11 16 12 88 44 4 4 10 16 24 160 40 449162414436 448162412832 447162411228 466162414424 485162816020 4 10 4 16 32 160 16 4 12 3 16 32 144 12
mb91460h series 76 ds07-16616-1e 2. clock modulator settings the following table shows all possible settings for the clock modulator in a base clock frequency range from 32mhz up to 88mhz. the flash access time settings need to be adjusted according to fmax while the pll and clockgear settings should be set according to base clock frequency. clock modulator settings, frequency range and supported supply voltage modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz] 1 3 026f 88 79.5 98.5 1 3 026f 84 76.1 93.8 1 3 026f 80 72.6 89.1 1 5 02ae 80 68.7 95.8 2 3 046e 80 68.7 95.8 1 3 026f 76 69.1 84.5 1 5 02ae 76 65.3 90.8 1 7 02ed 76 62 98.1 2 3 046e 76 65.3 90.8 3 3 066d 76 62 98.1 1 3 026f 72 65.5 79.9 1 5 02ae 72 62 85.8 1 7 02ed 72 58.8 92.7 2 3 046e 72 62 85.8 3 3 066d 72 58.8 92.7 1 3 026f 68 62 75.3 1 5 02ae 68 58.7 80.9 1 7 02ed 68 55.7 87.3 1 9 032c 68 53 95 2 3 046e 68 58.7 80.9 2 5 04ac 68 53 95 3 3 066d 68 55.7 87.3 4 3 086c 68 53 95 1 3 026f 64 58.5 70.7 1 5 02ae 64 55.3 75.9 1 7 02ed 64 52.5 82 1 9 032c 64 49.9 89.1 1 11 036b 64 47.6 97.6 2 3 046e 64 55.3 75.9 2 5 04ac 64 49.9 89.1
mb91460h series ds07-16616-1e 77 3 3 066d 64 52.5 82 4 3 086c 64 49.9 89.1 5 3 0a6b 64 47.6 97.6 1 3 026f 60 54.9 66.1 1 5 02ae 60 51.9 71 1 7 02ed 60 49.3 76.7 1 9 032c 60 46.9 83.3 1 11 036b 60 44.7 91.3 2 3 046e 60 51.9 71 2 5 04ac 60 46.9 83.3 3 3 066d 60 49.3 76.7 4 3 086c 60 46.9 83.3 5 3 0a6b 60 44.7 91.3 1 3 026f 56 51.4 61.6 1 5 02ae 56 48.6 66.1 1 7 02ed 56 46.1 71.4 1 9 032c 56 43.8 77.6 1 11 036b 56 41.8 84.9 1 13 03aa 56 39.9 93.8 2 3 046e 56 48.6 66.1 2 5 04ac 56 43.8 77.6 2 7 04ea 56 39.9 93.8 3 3 066d 56 46.1 71.4 3 5 06aa 56 39.9 93.8 4 3 086c 56 43.8 77.6 5 3 0a6b 56 41.8 84.9 6 3 0c6a 56 39.9 93.8 1 3 026f 52 47.8 57 1 5 02ae 52 45.2 61.2 1 7 02ed 52 42.9 66.1 1 9 032c 52 40.8 71.8 1 11 036b 52 38.8 78.6 1 13 03aa 52 37.1 86.8 1 15 03e9 52 35.5 96.9 2 3 046e 52 45.2 61.2 2 5 04ac 52 40.8 71.8 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
mb91460h series 78 ds07-16616-1e 2 7 04ea 52 37.1 86.8 3 3 066d 52 42.9 66.1 3 5 06aa 52 37.1 86.8 4 3 086c 52 40.8 71.8 5 3 0a6b 52 38.8 78.6 6 3 0c6a 52 37.1 86.8 7 3 0e69 52 35.5 96.9 1 3 026f 48 44.2 52.5 1 5 02ae 48 41.8 56.4 1 7 02ed 48 39.6 60.9 1 9 032c 48 37.7 66.1 1 11 036b 48 35.9 72.3 1 13 03aa 48 34.3 79.9 1 15 03e9 48 32.8 89.1 2 3 046e 48 41.8 56.4 2 5 04ac 48 37.7 66.1 2 7 04ea 48 34.3 79.9 3 3 066d 48 39.6 60.9 3 5 06aa 48 34.3 79.9 4 3 086c 48 37.7 66.1 5 3 0a6b 48 35.9 72.3 6 3 0c6a 48 34.3 79.9 7 3 0e69 48 32.8 89.1 1 3 026f 44 40.6 48.1 1 5 02ae 44 38.4 51.6 1 7 02ed 44 36.4 55.7 1 9 032c 44 34.6 60.4 1 11 036b 44 33 66.1 11 30 3 a a4 43 1 . 5 7 3 1 15 03e9 44 30.1 81.4 2 3 046e 44 38.4 51.6 2 5 04ac 44 34.6 60.4 2 7 04ea 44 31.5 73 2 9 0528 44 28.9 92.1 3 3 066d 44 36.4 55.7 3 5 06aa 44 31.5 73 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
mb91460h series ds07-16616-1e 79 4 3 086c 44 34.6 60.4 4 5 08a8 44 28.9 92.1 5 3 0a6b 44 33 66.1 6 3 0c6a 44 31.5 73 7 3 0e69 44 30.1 81.4 8 3 1068 44 28.9 92.1 1 3 026f 40 37 43.6 1 5 02ae 40 34.9 46.8 1 7 02ed 40 33.1 50.5 1 9 032c 40 31.5 54.8 1 11 036b 40 30 59.9 1 13 03aa 40 28.7 66.1 1 15 03e9 40 27.4 73.7 2 3 046e 40 34.9 46.8 2 5 04ac 40 31.5 54.8 2 7 04ea 40 28.7 66.1 2 9 0528 40 26.3 83.3 3 3 066d 40 33.1 50.5 3 5 06aa 40 28.7 66.1 3 7 06e7 40 25.3 95.8 4 3 086c 40 31.5 54.8 4 5 08a8 40 26.3 83.3 5 3 0a6b 40 30 59.9 6 3 0c6a 40 28.7 66.1 7 3 0e69 40 27.4 73.7 8 3 1068 40 26.3 83.3 9 3 1267 40 25.3 95.8 1 3 026f 36 33.3 39.2 1 5 02ae 36 31.5 42 1 7 02ed 36 29.9 45.3 1 9 032c 36 28.4 49.2 1 11 036b 36 27.1 53.8 1 13 03aa 36 25.8 59.3 1 15 03e9 36 24.7 66.1 2 3 046e 36 31.5 42 2 5 04ac 36 28.4 49.2 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
mb91460h series 80 ds07-16616-1e 2 7 04ea 36 25.8 59.3 2 9 0528 36 23.7 74.7 3 3 066d 36 29.9 45.3 3 5 06aa 36 25.8 59.3 3 7 06e7 36 22.8 85.8 4 3 086c 36 28.4 49.2 4 5 08a8 36 23.7 74.7 5 3 0a6b 36 27.1 53.8 6 3 0c6a 36 25.8 59.3 7 3 0e69 36 24.7 66.1 8 3 1068 36 23.7 74.7 9 3 1267 36 22.8 85.8 1 3 026f 32 29.7 34.7 1 5 02ae 32 28 37.3 1 7 02ed 32 26.6 40.2 1 9 032c 32 25.3 43.6 1 11 036b 32 24.1 47.7 11 30 3 a a3 22 3 5 2 . 5 1 15 03e9 32 22 58.6 2 3 046e 32 28 37.3 2 5 04ac 32 25.3 43.6 2 7 04ea 32 23 52.5 2 9 0528 32 21.1 66.1 2 11 0566 32 19.5 89.1 3 3 066d 32 26.6 40.2 3 5 06aa 32 23 52.5 3 7 06e7 32 20.3 75.9 4 3 086c 32 25.3 43.6 4 5 08a8 32 21.1 66.1 5 3 0a6b 32 24.1 47.7 5 5 0aa6 32 19.5 89.1 6 3 0c6a 32 23 52.5 7 3 0e69 32 22 58.6 8 3 1068 32 21.1 66.1 9 3 1267 32 20.3 75.9 10 3 1466 32 19.5 89.1 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
mb91460h series ds07-16616-1e 81 electrical characteristics 1. absolute maximum ratings *1 : the parameter is based on v ss 5 = av ss 5 = 0.0 v. parameter symbol rating unit remarks min max power supply slew rate ?? 50 v/ms power supply voltage 1* 1 v dd 5r - 0.3 + 6.0 v power supply voltage 2* 1 v dd 5 - 0.3 + 6.0v relationship of the supply volt- ages av cc 5 v dd 5-0.3 v dd 35-0.3 v dd 5+0.3 v dd 35+0.3 v at least one pin of the ports 26 to 29 (ann) is used as digital input or output. v ss 5-0.3 v dd 35-0.3 v dd 5+0.3 v dd 35+0.3 v all pins of the ports 26 to 29 (ann) follow the condition of v ia analog power supply voltage* 1 av cc 5 - 0.3 + 6.0v*2 analog reference power supply voltage* 1 avrh - 0.3 + 6.0 v *2 input voltage 1* 1 v i1 vss5 - 0.3 v dd 5 + 0.3 v analog pin input voltage* 1 v ia avss5 - 0.3 avcc5 + 0.3 v output voltage 1* 1 v o1 vss5 - 0.3 v dd 5 + 0.3 v maximum clamp current i clamp - 4.0 + 4.0 ma *3 total maximum clamp current |i clamp | ? 20 ma *3 ?l? level maximum output current* 4 i ol ? 10 ma ?l? level average output current* 5 i olav ? 8ma ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current* 6 i olav ? 50 ma ?h? level maximum output current* 4 i oh ? - 10 ma ?h? level average output current* 5 i ohav ? - 4 ma ?h? level total maximum output current i oh ? - 100 ma ?h? level total average output current* 6 i ohav ? - 25 ma power consumption p d ? 600 mw at t a = 105c operating temperature t a - 40 + 105 c storage temperature tstg - 55 + 150 c
mb91460h series 82 ds07-16616-1e *2 : av cc 5 and avrh5 must not exceed v dd 5 + 0.3 v. *3 : ? use within recommended operating conditions. ? use with dc voltage (current). ? +b signals are input signals that exceed the v dd 5 voltage. +b signals should always be applied by connecting a limiting resistor between the +b signal and the microcontroller. ? the value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed the rated value at any time , either instanta neously or for an extended period, when the +b signal is input. ? note that when the microcontroller drive current is low, such as in the low power consumption modes, the +b input potential can increase the potential at the powe r supply pin via a protective diode, possibly affecting other devices. ? note that if the +b signal is input when the microcontroller is off (not fixed at 0 v), power is supplied through the +b input pin; therefore, the microcontroller may partially operate. ? note that if the +b signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply voltage. ? do not leave +b input pins open. ? example of recommended circuit : *4 : maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5 : average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period. *6 : total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuit +b input (0 v to 16 v) limiting resistor protective diode
mb91460h series ds07-16616-1e 83 2. recommended operating conditions (v ss 5 = av ss 5 = 0.0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within thei r recommended operating condition ranges. operation outside these ranges ma y adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outsi de the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v dd 53.0 ? 5.5 v v dd 5r 3.0 ? 5.5 v internal regulator av cc 53.0 ? 5.5 v a/d converter smoothing capacitor at vcc18c pin c s ? 4.7 ? f use a x7r ceramic capacitor or a capacitor that has similar fre- quency characteristics. power supply slew rate ?? 50 v/ms operating temperature t a ? 40 ? + 105 c main oscillation stabilisation time 10 ms lock-up time pll (4 mhz ->16 ...100mhz) 0.6 ms esd protection (human body model) v surge 2k v r discharge = 1.5k c discharge = 100pf rc oscillator f rc100khz f rc2mhz 50 1 100 2 200 4 khz mhz vdd core > 1.65v c s avss5 vss5 vcc18c
mb91460h series 84 ds07-16616-1e 3. dc characteristics (v dd 5 = av cc 5 = 3.0 v to 5.5 v, v ss 5 = av ss 5 = 0 v, t a = -40 c to + 105 c) parameter symbol pin name condition value unit remarks min typ max input ?h? voltage v ih ? port inputs if cmos hysteresis 0.8/0.2 input is selected 0.8 v dd ? v dd + 0.3 v cmos hysteresis input ? port inputs if cmos hysteresis 0.7/0.3 input is selected 0.7 v dd ? v dd + 0.3 v 4.5 v < v dd < 5.5 v 0.74 v dd ? v dd + 0.3 v 3 v < v dd < 4.5 v ? automotive hysteresis input is selected 0.8 v dd ? v dd + 0.3 v ? port inputs if ttl input is selected 2.0 ? v dd + 0.3 v v ihr initx ? 0.8 v dd ? v dd + 0.3 v initx input pin (cmos hysteresis) v ihm md_3 to md_0 ? v dd - 0.3 ? v dd + 0.3 v mode input pins v ihx0s x0, x0a ? 2.5 ? v dd + 0.3 v external clock in ?oscillation mode? v ihx0f x0 ? 0.8 v dd ? v dd + 0.3 v external clock in ?fast clock input mode? input ?l? voltage v il ? port inputs if cmos hysteresis 0.8/0.2 input is selected v ss - 0.3 ? 0.2 v dd v ? port inputs if cmos hysteresis 0.7/0.3 input is selected v ss - 0.3 ? 0.3 v dd v ? port inputs if automotive hysteresis input is selected v ss - 0.3 ? 0.5 v dd v4.5 v < v dd < 5.5 v v ss - 0.3 ? 0.46 v dd v3 v < v dd < 4.5 v ? port inputs if ttl input is selected v ss - 0.3 ? 0.8 v v ilr initx ? v ss - 0.3 ? 0.2 v dd v initx input pin (cmos hysteresis) v ilm md_3 to md_0 ? v ss - 0.3 ? v ss + 0.3 v mode input pins v ilxds x0, x0a ? v ss - 0.3 ? 0.5 v external clock in ?oscillation mode?
mb91460h series ds07-16616-1e 85 parameter symbol pin name condition value unit remarks min typ max input ?l? voltage v ilxdf x0 ? v ss - 0.3 ? 0.2 v dd v external clock in ?fast clock input mode? output ?h? voltage v oh2 normal outputs 4.5v v dd 5.5v, i oh = - 2ma v dd - 0.5 ?? v driving strength set to 2 ma 3.0v v dd < 4.5v, i oh = - 1.6ma v oh5 normal outputs 4.5v v dd 5.5v, i oh = ? 5ma v dd - 0.5 ?? v driving strength set to 5 ma 3.0v v dd < 4.5v, i oh = - 3ma v oh3 i 2 c outputs 3.0v v dd 5.5v, i oh = - 3ma v dd - 0.5 ?? v output ?l? voltage v ol2 normal outputs 4.5v v dd 5.5v, i ol = + 2ma ?? 0.4 v driving strength set to 2 ma 3.0v v dd < 4.5v, i ol = + 1.6ma v ol5 normal outputs 4.5v v dd 5.5v, i ol = + 5ma ?? 0.4 v driving strength set to 5 ma 3.0v v dd < 4.5v, i ol = + 3ma v ol3 i 2 c outputs 3.0v v dd 5.5v, i ol = + 3ma ?? 0.4 v input leak- age current i il pnn_m * 1 3.0v v dd 5.5v v ss 5 < v i < v dd t a =25 c - 1 ? + 1 a 3.0v v dd 5.5v v ss 5 < v i < v dd t a =105 c - 3 ? + 3 analog in- put leak- age current i ain ann* 2 3.0v v dd 5.5v t a =25 c - 1 ? + 1 a 3.0v v dd 5.5v t a =105 c - 3 ? + 3 a pull-up resistance r up pnn_m * 3 initx 3.0v v dd 3.6v 40 100 160 k 4.5v v dd 5.5v 25 50 100 pull-down resistance r down pnn_m * 4 3.0v v dd 3.6v 40 100 180 k 4.5v v dd 5.5v 25 50 100
mb91460h series 86 ds07-16616-1e input capaci- tance c in all ex- cept v dd 5, v dd 5r, v ss 5, av cc 5, av ss 5, avrh5 f = 1 mhz - 5 15 pf power supply current mb91 f464hb i cc v dd 5r clkb: 100 mhz clkp: 50 mhz clkt: 50 mhz clkcan: 50 mhz - 100 130 ma code fetch from flash i cch v dd 5r t a = + 25 c - 30 150 a at stop mode *5 t a = + 105 c - 300 2000 a t a = + 25 c - 100 500 a rtc : 4 mhz mode *5 t a = + 105 c - 500 2400 a t a = + 25 c - 50 250 a rtc : 100 khz mode *5 t a = + 105 c - 400 2200 a i lve v dd 5 ?? 70 150 a external low volt- age detection i lvi v dd 5r ?? 50 100 a internal low volt- age detection i osc v dd 5 - - 250 500 a main clock (4 mhz) - - 20 40 a sub clock (32 khz) 1. pnn_m includes all gpio pins. analog (an) channels and pullup/pulldown are disabled. 2. ann includes all pins where an channels are enabled. 3. pnn_m includes all gpio pins. the pull up resistors must be enabled by pper/ppcr setting and the pins must be in input direction. 4. pnn_m includes all gpio pins. the pull down resi stors must be enabled by pper/ppcr setting and the pins must be in input direction. parameter symbol pin name condition value unit remarks min typ max
mb91460h series ds07-16616-1e 87 4. a/d converter characteristics (v dd 5 = = = = = ? + (continued) note : the accuracy gets worse as avrh - avrl becomes smaller parameter symbol pin name value unit remarks min typ max resolution ?? ? ? ?? ? ? + ?? ? ? + ?? ? ? + ? + + ? ? + ? ? ?? ? ?? ?? ? ?? ?? ?? ?? ?? ? ? + = + ? ? + = + ? ? ??
mb91460h series 88 ds07-16616-1e (continued) * 1 : supply current at av cc 5, if a/d converter and alarm comparator are not operating, (v dd 5 = av cc 5 = avrh = 5.0 v) * 2 : input current at avrh5, if a/ d converter is not operating, (v dd 5 = av cc 5 = avrh = 5.0 v) * 3 : the current consumption per adc macro is given here. on devices having more then one a/d converter, the current values have to be multiplied by the number of macros. sampling time calculation t samp = ( 2.6 kohm + r ext ) 11pf 7; for 4.5v av cc 5 5.5v t samp = (12.1 kohm + r ext ) 11pf 7; for 3.0v av cc 5 < 4.5v conversion time calculation t conv = t samp + t comp parameter symbol pin name value unit remarks min typ max reference voltage range avrh avrh5 0.75 av cc 5 ? av cc 5v avrl av ss 5av ss 5 ? av cc 5 0.25 v power supply current per adc macro * 3 i a av cc 5 ? 2.5 5 ma a/d converter active i ah av cc 5 ?? 5 a a/d converter not operated * 1 reference voltage current per adc macro * 3 i r avrh5 ? 0.7 1 ma a/d converter active i rh avrh5 ?? 5 a a/d converter not operated * 2
mb91460h series ds07-16616-1e 89 definition of a/d converter terms ? resolution analog variation that is rec ognizable by the a/d converter. ? nonlinearity error deviation between actual conversion characteristics an d a straight line connecting the zero transition point (00 0000 0000 b ? 00 0000 0001 b ) and the full scale transition point (11 1111 1110 b ? 11 1111 1111 b ). ? differential no nlinearity error deviation of the input voltage from the ideal value that is required to change the output code by 1 lsb. ? total error this error indicates the difference between actual and theoretical values, including the zero transition error, full scale transition error, and nonlinearity error. (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss 5 avrh 0.5 lsb' {1 lsb? (n - 1) + 0.5 lsb?} 1.5 lsb? analog input to ta l e r r o r digital output actual conversion characteristics v nt ( measurement value) ideal characteristics actual conversion characteristics total error of digital output n = 1 lsb' v nt ? {1 lsb' (n ? 1) + 0.5 lsb'} n : a/d converter digital output value v ot ' (ideal value) = av ss 5 + 0.5 lsb' [v] v fst ' (ideal value) = avrh ? 1.5 lsb' [v] v nt : voltage at which the digital output changes from (n + 1) h to n h 1lsb' (ideal value) = 1024 avrh ? av ss 5 [v]
mb91460h series 90 ds07-16616-1e (continued) (n+1) h n h (n-1) h (n-2) h av ss 5 avrh 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss 5 avrh {1 lsb (n - 1) + v ot } analog input analog input differential nonlinearity error nonlinearity error digital output digital output actual conversion characteristics v fst (measure- ment value) v nt (measure- ment value) actual conversion characteristics ideal characteristics v to (measurement value) actual conversion characteristics v nt (measure- ment value) v fst (measure- ment value) nonlinearity error of digital output n = 1lsb v nt ? {1lsb (n ? 1) + v ot } [lsb] differential nonlinearity error of digital output n = 1lsb v ( n + 1 ) t ? v nt ? 1 [lsb] 1lsb = 1022 v fst ? v ot [v] n : a/d converter digital output value v ot : voltage at which the digital output changes from 000 h to 001 h . v fst : voltage at which the digital output changes from 3fe h to 3ff h . actual conversion characteristics ideal characteristics
mb91460h series ds07-16616-1e 91 5. alarm comparator characteristics note: *1 : the fast alarm comparator mode is enabled by setting acsr.md=1 setting acsr.md=0 sets the normal mode. parameter symbol pin name value unit remarks min typ max power supply current i a5almf av cc 5 ? 25 40 a alarm compar- ator enabled in fast mode (per channel) *1 i a5alms ? 710 a alarm compar- ator enabled in normal mode (per channel) *1 i a5almh ?? 5 a alarm compar- ator disabled alarm pin in- put current i alin alarm_n - 1 ? + 1 at a =25 c - 3 ? + 3 at a =105 c alarm pin in- put voltage range v alin 0 ? av cc 5v alarm upper limit voltage v iah av cc 5 0.78 - 3% av cc 5 0.78 av cc 5 0.78 + 3% v alarm lower limit voltage v ial av cc 5 0.36 - 5% av cc 5 0.36 av cc 5 0.36 + 5% v alarm hystere- sis voltage v iahys 50 ? 250 mv alarm input resistance r in 5 ?? m comparion time t compf ? 0.1 0.2 s alarm compar- ator enabled in fast mode *1 t comps ? 12 s alarm compar- ator enabled in normal mode *1
mb91460h series 92 ds07-16616-1e 6. flash memory program/erase characteristics 6.1. MB91F464HB ( t a = 25 o c , vcc = 5.0v) *1: this value was converted from the results of evaluati ng the reliability of the te chnology (using arrhenius equation to convert high temperature measurements into normalized value at 85 o c) parameter value unit remarks min typ max sector erase time - 0.9 3.6 s erasure programming time not included chip erase time - n*0.9 n*3.6 s n is the number of flash sector of the device word (16-bit or 32-bit width) programming time -23370 s system overhead time not in- cluded programme/erase cycle 10 000 cycle flash data retention time 20 year *1
mb91460h series ds07-16616-1e 93 7. ac characteristics 7.1. clock timing (v dd 5 = 3.0 v to 5.5 v, vss5 = avss5 = 0 v, t a = -40 c to + 105 c) ? clock timing condition 7.2. reset input ratings (v dd 5 = 3.0 v to 5.5 v, v ss 5 = av ss 5 = 0 v, t a = -40 c to + 105 c) parameter symbol pin name value unit condition min typ max clock frequency f c x0 x1 3.5 4 16 mhz opposite phase external supply or crystal x0a x1a 32 32.768 100 khz parameter symbol pin name condition value unit min max initx input time (at power-on) t intl initx ? 8 ? ms initx input time (other than the above) 20 ? s 0.8 v cc 0.2 v cc p wh p wl t c x0, x1, x0a, x1a 0.2 v cc t intl initx
mb91460h series 94 ds07-16616-1e 7.3. lin-usart timings at v dd 5 = 3.0 to 5.5 v ? conditions during ac measurements all ac tests were measured under the following conditions: - io drive = 5 ma - v dd 5 = 3.0 v to 5.5 v, i load = 3 ma - v ss 5 = 0 v - t a = -40 c to +105 c - c l = 50 pf (load capacity value of pins when testing) - vol = 0.2 x v dd 5 - voh = 0.8 x v dd 5 - epilr = 0, pilr = 1 (automotive level = worst case) (v dd 5 = 3.0 v to 5.5 v, v ss 5 = av ss 5 = 0 v, t a = -40 c to + 105 c) * : parameter m depends on t scyci and can be calculated as : ? if t scyci = 2*k*t clkp , then m = k, where k is an integer > 2 ? if t scyci = (2*k + 1)*t clkp , then m = k + 1, where k is an integer > 1 notes : ? the above values are ac characteristics for clk synchronous mode. ? t clkp is the cycle time of the peripheral clock. parameter symbol pin name condition v dd 5 = 3.0 v to 4.5 v v dd 5 = 4.5 v to 5.5 v unit min max min max serial clock cycle time t scyci sckn internal clock operation (master mode) 4 t clkp ? 4 t clkp ? ns sck sot delay time t slovi sckn sotn - 30 30 - 20 20 ns sot sck delay time t ovshi sckn sotn m t clkp - 30* ? m t clkp - 20* ? ns valid sin sck setup time t ivshi sckn sinn t clkp + 55 ? t clkp + 45 ? ns sck valid sin hold time t shixi sckn sinn 0 ? 0 ? ns serial clock ? h? pulse width t shsle sckn external clock operation (slave mode) t clkp + 10 ? t clkp + 10 ? ns serial clock ? l? pulse width t slshe sckn t clkp + 10 ? t clkp + 10 ? ns sck sot delay time t slove sckn sotn ? 2 t clkp + 55 ? 2 t clkp + 45 ns valid sin sck setup time t ivshe sckn sinn 10 ? 10 ? ns sck valid sin hold time t shixe sckn sinn t clkp + 10 ? t clkp + 10 ? ns sck rising time t fe sckn ? 20 ? 20 ns sck falling time t re sckn ? 20 ? 20 ns
mb91460h series ds07-16616-1e 95 ? internal clock mode (master mode) ? external clock mode (slave mode) t ivshi v ih t shixi t s lovi t scyci v ol s otn sckn for e scr:sces = 0 sckn for e scr:sces = 1 t ov shi v ol v ol v il v ol v il v ih v oh v oh v oh v oh sinn t ivshe v ih t shixe t s love t slshe v ol s otn sckn for e scr:sces = 0 sckn for e scr:sces = 1 v ol v il v ol v il v ih v oh v oh v ol v oh v oh v oh sinn t shsle v ol t re v oh t fe v ol
mb91460h series 96 ds07-16616-1e 7.4. i 2 c ac timings at v dd 5 = 3.0 to 5.5 v ? conditions during ac measurements all ac tests were measured under the following conditions: -io drive = 3 ma -v dd 5 = 3.0 v to 5.5 v, i load = 3 ma -v ss 5 = 0 v - ta = - 40 c to + 105 c -c l = 50 pf - vol = 0.3 v dd 5 - voh = 0.7 v dd 5 - epilr = 0, pilr = 0 (cmos hysteresis 0.3 v dd 5/0.7 v dd 5) fast mode: (v dd 5 = 3.5 v to 5.5 v, v ss 5 = av ss 5 = 0 v, t a = -40 c to + 105 c) * 1 the noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase relationship between i 2 c signals (sda, scl) and peripheral clock. note: t clkp is the cycle time of the peripheral clock. parameter symbol pin name value unit remark min max scl clock frequency f scl scln 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta scln, sdan 0.6 ? s low period of the scl clock t low scln 1.3 ? s high period of the scl clock t high scln 0.6 ? s setup time for a repeated start condition t su;sta scln, sdan 0.6 ? s data hold time for i 2 c-bus devices t hd;dat scln, sdan 0 0.9 s data setup time t su;dat scln sdan 100 ? ns rise time of both sda and scl signals t r scln, sdan 20 + 0.1cb 300 ns fall time of both sda and scl signals t f scln, sdan 20 + 0.1cb 300 ns setup time for stop condition t su;sto scln, sdan 0.6 ? s bus free time between a stop and start condition t buf scln, sdan 1.3 ? s capacitive load for each bus line c b scln, sdan ? 400 pf pulse width of sp ike suppressed by input filter t sp scln, sdan 0 (1..1.5) t clkp ns * 1
mb91460h series ds07-16616-1e 97 sda s sr p s scl t hd;sta tr tr t sp t su;st0 t su;sta t su;dat t hd;dat t hd;sta t low t high t buf tf tf
mb91460h series 98 ds07-16616-1e 7.5. free-run timer clock (v dd 5 = 3.0 v to 5.5 v, v ss 5 = av ss 5 = 0 v, t a = -40 c to + 105 c) note : t clkp is the cycle time of the peripheral clock. 7.6. trigger input timing (v dd 5 = 3.0 v to 5.5 v, v ss 5 = av ss 5 = 0 v, t a = -40 c to + 105 c) note : t clkp is the cycle time of the peripheral clock. parameter symbol pin name condition value unit min max input pulse width t tiwh t tiwl ckn ? 4t clkp ? ns parameter symbol pin name condition value unit min max input capture input trigger t inp icun ? 5t clkp ? ns a/d converter trigger t atgx atgx ? 5t clkp ? ns t tiwh t tiwl ckn v ih v ih v il v il icun, atgx t atgx, t inp
mb91460h series ds07-16616-1e 99 7.7. external bus ac timings at v dd 35 = 3.0 to 5.5 v ? conditions during ac measurements all ac tests were measured under the following conditions: -io drive = 5 ma -v dd 35 = 4.5 v to 5.5 v, i load = 3 ma -v ss 5 = 0 v - ta = - 40 c to + 105 c -c l = 50 pf - vol = 0.5 v dd 35 - voh = 0.5 v dd 35 - epilr = 0, pilr = 1 (automotive level = worst case) 7.7.1. basic timing (v dd 35 = 3.0 v to 5.5 v, vss5 = avss5 = 0 v, t a = -40 c to + 105 c) note : t clkt is the cycle time of the external bus clock. parameter symbol pin name value unit min max sysclk t clch sysclk 1/2 t clkt - 1 1/2 t clkt + 9 ns t chcl 1/2 t clkt - 9 1/2 t clkt + 1 ns sysclk to csxn delay time t clcsl sysclk csxn ? 8ns t clcsh ? 12 ns sysclk to csxn delay time (addr cs delay) t chcsl - 6 + 1 ns sysclk to address valid delay time t clav sysclk a21 to a0 ? 13 ns
mb91460h series 100 ds07-16616-1e sysclk csxn delayed csxn asx address baax t chcsl t clasl t clav t clbal t clash t clcsl t clch t chcl t cyc t clcsh t clbah
mb91460h series ds07-16616-1e 101 7.7.2. synchronous/asynchronous read access (v dd 35 = 3.0 v to 5.5 v, vss5 = avss5 = 0 v, t a = -40 c to + 105 c) parameter symbol pin name value unit min max sysclk to rdx delay time tchrl sysclk rdx - 7 1 ns tchrh - 4 2 ns data valid to rdx setup time tdsrh rdx d31 to d16 33 ? ns rdx to data valid hold time trhdx rdx d31 to d16 0 ? ns sysclk to wrxn (as byte enable) delay time tclwrl sysclk wrxn ? 8ns tclwrh 0 ? ns sysclk to csxn delay time tclcsl sysclk csxn ? 8ns tclcsh ? 12 ns sysclk csxn wrxn (as byte enable) rdx data in t dsrh t rhdx t chrh t chrl t clwrl t clwrh t clcsh t clcsl
mb91460h series 102 ds07-16616-1e 7.7.3. synchronous write access (v dd 35 = 3.0 v to 5.5 v, vss5 = avss5 = 0 v, t a = -40 c to + 105 c) parameter symbol pin name value unit min max sysclk to wrxn delay time tclwrl sysclk wrxn ? 8ns tclwrh 0 ? ns data valid to wrxn setup time tdswrl wrxn d31 to d16 - 7 ? ns wrxn to data valid hold time twrhdh wrxn d31 to d16 t clkt - 20 ? ns sysclk to csxn delay time tclcsl sysclk csxn ? 8ns tclcsh ? 12 ns sysclk csxn wrxn data out t clwrh t clwrl t dswrl t wrhdh t clcsh t clcsl
mb91460h series ds07-16616-1e 103 7.7.4. asynchronous write access (v dd 35 = 3.0 v to 5.5 v, vss5 = avss5 = 0 v, t a = -40 c to + 105 c) parameter symbol pin name value unit min max wrxn to wrxn pulse width twrlwrh wrxn t clkt ? ns data valid to wrxn setup time tdswrl wrxn d31 to d16 1/2 t clkt - 10 ? ns wrxn to data valid hold time twrhdh wrxn d31 to d16 1/2 t clkt - 19 ? ns wrxn to csxn delay time tclwrl wrxn csxn ? 1/2 t clkt ns twrhch 1/2 t clkt ? ns csxn wrxn data out twrhdh twrhch tclwrl twrlwrh tdswrl
mb91460h series 104 ds07-16616-1e 7.7.5. rdy waitcycle insertion (v dd 35 = 3.0 v to 5.5 v, vss5 = avss5 = 0 v, t a = -40 c to + 105 c) parameter symbol pin name value unit min max rdy setup time trdys sysclk rdy 34 ? ns rdy hold time trdyh sysclk rdy 0 ? ns sysclk rdy t rdys t rdyh
mb91460h series ds07-16616-1e 105 ordering information part number package remarks MB91F464HBpmc-gse2 144-pin plastic lqfp (fpt-144p-m08) lead-free package
mb91460h series 106 ds07-16616-1e package dimension please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ 144-pin plastic lqfp lea d pitch 0.50 mm p a ck a ge width p a ck a ge length 20.0 20.0 mm lea d s h a pe gu llwing s e a ling method plastic mold mounting height 1.70 mm max weight 1.20g code (reference) p-lfqfp144-20 20-0.50 144-pin plastic lqfp (fpt-144p-m0 8 ) (fpt-144p-m08) c 2003 fujitsu limited f144019s-c-4-6 details of "a" part 0.25(.010) (stand off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.008) 0.500.20 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ? ~8 ? 0.50(.020) "a" 0.08(.003) 0.1450.055 (.006.002) lead no. 1 36 index 37 72 73 108 109 144 0.220.05 (.009.002) m 0.08(.003) 20.000.10(.787.004)sq 22.000.20(.866.008)sq (mounting height) * dimens ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . ?2003 -2008 fujits u microelectronics limited f144019s -c-4-7 note 1) * :values do not include resin protrusion. res in protrusion is +0.25(.010)ma x(ea ch s ide). note 2) pin s width and pins thickness include plating thickness. note 3 )pin s width do not include tie bar cutting remainder.
mb91460h series ds07-16616-1e 107 revision history version date remark 2.0 2009-01-07 initial version
mb91460h series 108 ds07-16616-1e main changes in this edition the vertical lines marked in the left side of the page show the changes. page section change results 87 4. a/d converter characteristics corrected "zero reading voltage" and "full scale reading voltage".
mb91460h series ds07-16616-1e 109 memo
mb91460h series 110 ds07-16616-1e memo
mb91460h series ds07-16616-1e 111 memo
mb91460h series fujitsu microelectronics limited shinjuku dai-ichi seimei bldg., 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu. com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu microelectronics asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fmal.fujitsu.com/ fujitsu microelectronics shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectroni cs pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further inform ation please cont act each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representative s before ordering. the information, such as descri ptions of function and applicati on circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of ope rations and uses of fujits u microelectronics device; fujitsu microelectronics does not warrant proper operation of the de vice with respect to use based on such information. when you develop equipment incor porating the device based on such inform ation, you must assume any responsibility arising out of su ch use of the information. fujitsu microelectronics assumes no liab ility for any damages whatsoever arisi ng out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microel ectronics warrant non-infringeme nt of any third-party's intellectual property right o r other right by using such information. fu jitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of in formation cont ained herein. the products described in this document are designed, developed and manufa ctured as contemplated fo r general use, including wit hout limitation, ordinary indus trial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead direct ly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction con trol in nuclear facility, aircraft flight control, air traffic control, mass tr ansport control, medical life s upport system, missile launch con trol in weapon system), or (2) for use requiring extrem ely high reliability (i.e., submersibl e repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any th ird party for any clai ms or damages arisi ng in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of ov er-current levels and other abnor mal operating conditions. exportation/release of any products described in this docum ent may require necessary procedures in accordance with the regulations of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand na mes herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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